Xilinx LogiCORE Getting Started Manual page 29

Directory Structure and File Descriptions
<project_dir>/implement/results
This directory is produced by the implementation scripts and is used to run through the
example design and the core through the Xilinx implementation tools. Once the implement
script has completed it contains the following files for timing simulation.
routed.v
The back-annotated simprim based Verilog model used for timing simulation. This is
SimPrim-based.
routed.sdf
The timing information for simulation is contained in this file.
<project_dir>/<component_name>/simulation
The simulation directory and subdirectories provide the files you need to test a Verilog
implementation of the example design.
demo_tb.v
The Verilog demonstration test bench file for the example design. See the following
sections in this document for more information.
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•
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<project_dir>/<component_name>/simulation/functional
simulate_mti.do
A ModelSim macro file that compiles the Verilog sources and then runs the functional
simulation to completion.
wave_mti.do
A ModelSim macro file that opens a wave window and adds signals of interest to it. It is
called by the simulate_mti.do macro file.
simulate_ncsim.sh
An IUS script file that compiles the Verilog sources and runs the functional simulation to
completion.
wave_ncsim.sv
An IUS macro file that opens a wave window and adds signals of interest to it. It is called
by the simulate_ncsim.sh script file.
<project_dir>/<component_name>/simulation/timing
Note:
simulate_mti.do
A ModelSim macro file that compiles the Verilog sources and then runs the timing
simulation to completion.
wave_mti.do
Ethernet 1000BASE-X PCS/PMA or SGMII v7.0
UG145 January 18, 2006
"Core Example Design Using RocketIO," page 32
"Core Example Design with Ten-Bit Interface," page 36
"SGMII Example Design / Dynamic Switching Example Design," page 40
This directory is only present with the Full license.
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