Implementation Scripts; Simulation Scripts; Functional Simulation - Xilinx LogiCORE Getting Started Manual

Ethernet 1000base-x pcs/pma or sgmii v7.0
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R
A ModelSim macro file that opens a wave window and adds signals of interest to it. It is
called by the simulate_mti.do macro file.
simulate_ncsim.sh
An IUS script file that compiles the Verilog sources and then runs the timing simulation to
completion.
wave_ncsim.sv
An IUS macro file that opens a wave window and adds signals of interest to it. It is called
by the simulate_ncsim.sh script file.

Implementation Scripts

Note:
The implementation script is either a shell script or batch file that processes the example
design through the Xilinx tool flow. It is located at:
UNIX:
Windows:
The implement script performs the following steps:
1.
2.
3.
4.
5.
6.
7.
The Xilinx tool flow generates several output and report files. These are saved in the
following directory which is created by the implement script:

Simulation Scripts

Functional simulation

The test script is a ModelSim or an IUS macro that automates the simulation of the test
bench. It is located at:
The test script performs the following tasks:
30
These scripts are only present with the Full license.
<project_dir>/<component_name>/implement/implement.sh
<project_dir>/<component_name>/implement/implement.bat
The HDL example design files are synthesized using XST.
Ngdbuild is run to consolidate the core netlist and the example design netlist into the
NGD file containing the entire design.
The design is mapped to the target technology.
The design is placed-and-routed on the target device.
Static timing analysis is performed on the routed design using trce.
A bitstream is generated.
Netgen runs on the routed design to generate a VHDL or Verilog netlist (as
appropriate for the Design Entry project setting) and timing information in the form of
SDF files.
<project_dir>/<component_name>/implement/results
<project_dir>/<component_name>/simulation/functional/
Compiles the structural UNISIM simulation model
www.xilinx.com
Chapter 4: Detailed Example Design
Ethernet 1000BASE-X PCS/PMA or SGMII v7.0
UG145 January 18, 2006

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