Directory Structure And File Descriptions; Vhdl Design Entry - Xilinx LogiCORE Getting Started Manual

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Detailed Example Design
This chapter provides detailed information about the Ethernet 1000BASE-X PCS/PMA or
SGMII example design, including a description of files and the directory structure
generated by the Xilinx CORE Generator, the purpose and contents of the provided scripts,
the contents of the example HDL wrappers, and the demonstration test bench.

Directory Structure and File Descriptions

VHDL Design Entry

Figure 4-1
Design Entry Project. In this example, <project_dir> is the CORE Generator project
directory; <component_name> is the component name as entered in the core customization
window.
Note:
Ethernet 1000BASE-X PCS/PMA or SGMII v7.0
UG145 January 18, 2006
shows the files and directories created by CORE Generator system in a VHDL
The implement and simulation/timing directories are only present with a Full license.
<component_name>.ngc
<component_name>.vhd
<component_name>.vho
<component_name>.xco
<component_name>.xcp
<component_name>_flist.txt
implement.bat
implement.sh
xst.scr
xst.prj
Generated by the implement scripts
Contains the back-annotated vhdl
netlist files.
demo_tb.vhd
Figure 4-1: Core Directories and Files
www.xilinx.com
<project_dir>
gig_eth_pcs_pma_v7_0_
release_notes.txt
<component_name> gig_eth_pcs_pma_ds264.pdf
gig_eth_pcs_pma_gsg145.pdf
gig_eth_pcs_pma_ug155.pdf
doc
<component_name>_top.vhd
example_design
<component_name>_top.ucf
Other Example Design VHDL
files
implement
results
simulation simulate_mti.do
wave_mti.do
functional
simulate_ncsim.sh
wave_ncsim.sv
simulate_mti.do
timing
wave_mti.do
simulate_ncsim.sh
wave_ncsim.sv
Chapter 4
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