Receiver Rate Adaptation Module - Xilinx LogiCORE Getting Started Manual

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The Johnson Counter is instantiated twice by the clock generation circuitry. The Johnson
Counter is a shift register based clock divider that provides a divide-by-ten clock output.
The divide-by-ten clock is output directly from a flip-flop triggered on the rising edge of
the 125 MHz reference clock, clk125m.
Johnson Counter capabilities are extended by using the clock enables; it is only the clock-
enabled cycles that trigger the shift register, and are therefore divided down.
Transmitter Rate Adaptation Module
The Transmitter Rate Adaptation module is described in the following files:
VHDL
Verilog
This module accepts transmitter data from the GMII-style interface from the attached
client MAC, and samples the input data on the 125 MHz reference clock, clk125m. This
sampled data can then be connected directly to the input GMII of the Ethernet 1000BASE-
X PCS/PMA or SGMII core. The 1 Gbps and 100 Mbps cases are illustrated in
At 1 Gbps the client MAC should drive the GMII transmitter data synchronously to the
rising edge of clk125m. sgmii_clk_en_fall (derived from the Clock Generation
module) is fixed at logic 1 and the input data is sampled on every clock cycle.
At 100 Mbps and 10 Mbps, the client MAC should drive the GMII transmitter data
synchronously to the rising edge of sgmii_clk. The data is sampled (see
the sgmii_clk_en_fall pulse. Since this pulse marks the falling edge of sgmii_clk,
it guarantees that the data is stable when sampled. The frequency of the
sgmii_clk_en_fall pulse ensures that this data is repeated exactly 10 times when
operating at a speed of 100 Mbps and 100 times when operating at a speed of 10 Mbps.
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project_dir>/<component_name>/example_design/sgmii_adapt/
tx_rate_adapt.vhd
project_dir>/<component_name>/example_design/sgmii_adapt/
tx_rate_adapt.v
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Chapter 4: Detailed Example Design
Ethernet 1000BASE-X PCS/PMA or SGMII v7.0
UG145 January 18, 2006
Figure 4-10.
Figure 4-10) on