Xilinx LogiCORE Getting Started Manual page 28

R
A test file listing all of the output files produced when a customized core is generated by
CORE Generator.
<project_dir>/<component_name>
gig_eth_pcs_pma_v7_0_release_notes.txt
The Ethernet 1000BASE-X PCS/PMA or SGMII core release notes text document.
<project_dir>/<component_name>/doc
This directory contains documentation for the core.
gig_eth_pcs_pma_ds264.pdf
This is the Xilinx Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 Data Sheet.
gig_eth_pcs_pma_gsg145.pdf
This is the Xilinx Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 Getting Started Guide.
gig_eth_pcs_pma_ug155.pdf
This is the Xilinx Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 User Guide.
<project_dir>/<component_name>/example_design
This directory contains the support files necessary for a Verilog implementation of the
example design.
<component_name>_top.v
This file is the top-level Verilog file for the example design. Other Verilog design files may
also be present. Please see the following for more information.
•
•
•
<project_dir>/implement
Note:
implement.sh
A UNIX shell script that processes the example design through the Xilinx tool flow. See
"Implementation Scripts," page 30
implement.bat
A Windows batch file that process the example design through the Xilinx tool flow. See
"Implementation Scripts," page 30
xst.prj
The XST project file for the example design. It enumerates all of the Verilog files that need
to be synthesized.
xst.scr
The XST script file for the example design.
28
"Core Example Design Using RocketIO," page 32
"Core Example Design with Ten-Bit Interface," page 36
"SGMII Example Design / Dynamic Switching Example Design," page 40
This directory is only present with the Full license.
www.xilinx.com
Chapter 4: Detailed Example Design
for more information.
for more information.
Ethernet 1000BASE-X PCS/PMA or SGMII v7.0
UG145 January 18, 2006