Xilinx LogiCORE Getting Started Manual page 24

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Project Directory (<project_dir>)
<component_name>.ngc
The Xilinx netlist for the core. This is instantiated by the VHDL example design.
<component_name>.vhd
The VHDL simulation model used to support the VHDL functional simulation of the core.
This is UNISIM based.
<component_name>.vho
This contains a VHDL instantiation template for the core.
<component_name>.xco
A log file that records the settings used to generate a core. An XCO file is generated by the
CORE Generator for each core that it creates in the current project directory. An XCO file
can also be used as an input to the CORE Generator.
<component_name>.xcp
Similar to the XCO file except that it does not specify project-specific settings, such as
target architecture and output products.
<component_name>_flist.txt
A test file listing all of the output files produced when a customized core is generated by
CORE Generator.
<project_dir>/<component_name>
gig_eth_pcs_pma_v7_0_release_notes.txt
The Ethernet 1000BASE-X PCS/PMA or SGMII core release notes text document.
<project_dir>/<component_name>/doc
This directory contains the following documentation for this core.
gig_eth_pcs_pma_ds264.pdf
This is the Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 Data Sheet.
gig_eth_pcs_pma_gsg145.pdf
This is the Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 Getting Started Guide.
gig_eth_pcs_pma_ug155.pdf
This is the Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 User Guide.
<project_dir>/<component_name>/example_design
This directory contains the support files you need for a VHDL implementation of the
example design.
<component_name>_top.vhd
This file is the top-level VHDL file for the example design. Other VHDL design files may
also be present. Please see the following sections for more information.
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24
"Core Example Design Using RocketIO," page
www.xilinx.com
Chapter 4: Detailed Example Design
32.
Ethernet 1000BASE-X PCS/PMA or SGMII v7.0
UG145 January 18, 2006