Timing Simulation; What's Next - Xilinx LogiCORE Getting Started Manual

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To run a VHDL or Verilog functional simulation of the example design:
1.
2.
The simulation script compiles the functional simulation model, the example design files,
the demonstration test bench, and adds relevant signals to a wave window. It then runs the
simulation to completion. After completion, you can inspect the simulation transcript and
waveform to observe the operation of the core.

Timing Simulation

Note:
This section contains instructions for running a timing simulation or the Ethernet
1000BASE-X PCS/PMA or SGMII core using either VHDL or Verilog. A timing simulation
model is generated when run through the Xilinx tools using the implementation script.
You must implement the core before attempting to run timing simulation.
To run a VHDL or Verilog timing simulation of the example design:
1.
2.
3.
The simulator script compiles the gate-level model and the demonstration test bench, adds
relevant signals to a wave window, and then runs the simulation to completion. You can
then inspect the simulation transcript and waveform to observe the operation of the core.

What's Next?

For detailed information about the example design, including guidelines for modifying the
design and extending the test bench, see
To begin using the Ethernet 1000BASE-X PCS/PMA or SGMII core in your own designs,
see the Xilinx Ethernet 1000BASE-X PCS/PMA or SGMII User Guide.
22
Open a command prompt or shell, then set the current directory to:
<project_dir>/<component_name>/simulation/functional/
Launch the simulation script:
ModelSim: vsim -do simulate_mti.do
IUS: ./simulate_ncsim.sh
Available only with a Full license.
Run the implementation script (see
Open a command prompt or shell, then set the current directory to:
<project_dir>/<component_name>/simulation/timing/
Launch the simulation script:
ModelSim: vsim -do simulate_mti.do
IUS: ./simulate_ncsim.sh
www.xilinx.com
Chapter 3: Quick Start Example Design
"Implementing the Example
Chapter 4, "Detailed Example Design."
Ethernet 1000BASE-X PCS/PMA or SGMII v7.0
Design").
UG145 January 18, 2006