Transmitter Rate Adaptation Module - Xilinx LogiCORE Getting Started Manual

SGMII Example Design / Dynamic Switching Example Design
Figure 4-9
Speed is 1 Gbps
Speed is 100 Mbps
Johnson Counter
The Johnson Counter is described in the following files:
VHDL
Verilog
Ethernet 1000BASE-X PCS/PMA or SGMII v7.0
UG145 January 18, 2006
shows the clock generator output clocks and clock enable configurations.
clk125 m
'1'
sgmii_clk_en_fall
sgmii_clk_r
'0'
'1'
sgmii_clk_f
sgmii_clk
(result of IOB
output DDR)
clk125 m
sgmii_clk_en_fall
sgmii_clk_r
sgmii_clk_f
sgmii_clk
(result of IOB
output DDR)
Figure 4-9: Clock Generator Output Clocks and Clock Enable
project_dir>/<component_name>/example_design/sgmii_adapt/
johnson_cntr.vhd
project_dir>/<component_name>/example_design/sgmii_adapt/
johnson_cntr.v
www.xilinx.com
10 clk125 m
cycles
5 clk125 m
cycles
R
45