Counter And Prescaler - Epson S1C63616 Technical Manual

4.8.3 Counter and prescaler

The stopwatch timer is configured of four-bit BCD counters SWD0–3, SWD4–7 and SWD8–11.
The counter SWD0–3, at the stage preceding the stopwatch timer, has a 1,000 Hz signal generated by the
prescaler for the input clock. It counts up every 1/1,000 sec, and generates 100 Hz signal. The counter
SWD4–7 has a 100 Hz signal generated by the counter SWD0–3 for the input clock. It count-up every
1/100 sec, and generated 10 Hz signal. The counter SWD8–11 has an approximated 10 Hz signal generated
by the counter SWD4–7 for the input clock. It count-up every 1/10 sec, and generated 1 Hz signal.
The prescaler inputs a 1,024 Hz clock dividing f
1,000 Hz counting clock for SWD0–3. To generate a 1,000 Hz clock from 1,024 Hz, 24 pulses from 1,024
pulses that are input to the prescaler every second are taken out.
When the counter becomes the value indicated below, one pulse (1,024 Hz) that is input immediately after
to the prescaler will be pulled out.
<Counter value (msec) in which the pulse correction is performed>
39, 79, 139, 179, 219, 259, 299, 319, 359, 399, 439, 479, 539, 579, 619, 659, 699, 719, 759, 799, 839, 879, 939, 979
Figure 4.8.3.1 shows the operation of the prescaler.
Prescaler input clock (1,024 Hz)
Prescaler output clock
Counter data
For the above reason, the counting clock is 1,024 Hz (0.9765625 msec) except during pulse correction.
Consequently, frequency of the prescaler output clock (1,000 Hz), 100 Hz generated by SWD0–3 and 10 Hz
generated by SWD4–7 are approximate values.
4.8.4 Capture buffer and hold function
The stopwatch data, 1/1,000 sec, 1/100 sec and 1/10 sec, can be read from SWD0–3 (FF4BH), SWD4–
7 (FF4CH) and SWD8–11 (FF4DH), respectively. The counter data are latched in the capture buffer when
reading, and are held until reading of three words is completed. For this reason, correct data can be read
even when a carry from lower digits occurs during reading the three words. Further, three counter data are
latched in the capture buffer at the same time when SWD0–3 (1/1,000 sec) is read. The data hold is released
when SWD8–11 (1/10 sec) reading is completed. Therefore, data should be read in order of SWD0–3 →
SWD4–7 → SWD8–11. If SWD4–7 or SWD8–11 is first read when data have not been held, the hold function
does not work and data in the counter is directly read out. When data that has not been held is read in the
stopwatch timer RUN status, you cannot judge whether it is correct or not.
The stopwatch timer has a LAP function using an external key input (explained later). The capture buffer
is also used to hold LAP data. In this case, data is held until SWD8–11 is read. However, when a LAP input
is performed before completing the reading, the content of the capture buffer is renewed at that point.
Remaining data that have not been read become invalid by the renewal, and the hold status is not released
if SWD8–11 is read. When SWD8–11 is read after the capture buffer is updated, the capture renewal flag
CRNWF is set to "1" at that point. In this case, it is necessary to read from SWD0–3 again. The capture
renewal flag is renewed by reading SWD8–11.
Figure 4.8.4.1 shows the timing for data holding and reading.
(output from the OSC1 oscillation circuit), and outputs
OSC1
START
000 001 002
Fig. 4.8.3.1 Timing of the prescaler operation
SIC63616-(Rev. 1.0) NO. P85
037 038 039 040 041
3240-0412