Table of Contents
Advertisement
TMRUN: Clock timer Run/Stop control register (FF40H•D0)
Controls run/stop of the clock timer.
When "1" is written: Run
When "0" is written: Stop
Reading: Valid
The clock timer starts running when "1" is written to the TMRUN register, and stops when "0" is written.
In stop status, the timer data is maintained until the next run status or the timer is reset. Also, when stop
status changes to run status, the data that is maintained can be used for resuming the count.
At initial reset, this register is set to "0".
TMRST: Clock timer reset (FF40H•D1)
This bit resets the clock timer.
When "1" is written: Clock timer reset
When "0" is written: No operation
Reading: Always "0"
The clock timer is reset by writing "1" to TMRST. When the clock timer is reset in run status, counting
restarts immediately. Also, in stop status the reset data is maintained. No operation results when "0" is
written to TMRST.
This bit is write-only, and so is always "0" at reading.
TM0–TM7: Timer data (FF41H, FF42H)
The 128–1 Hz timer data of the clock timer can be read out with these registers. These eight bits are read
only, and writing operations are invalid.
By reading the low-order data (FF41H), the high-order data (FF42H) is latched. The latched value, not the
current value, is always read as the high-order data. Therefore, be sure to read the low-order data first.
At initial reset, the timer data is initialized to "00H".
EIT0: 128 Hz interrupt mask register (FFEEH•D0)
EIT1: 64 Hz interrupt mask register (FFEEH•D1)
EIT2: 32 Hz interrupt mask register (FFEEH•D2)
EIT3: 16 Hz interrupt mask register (FFEEH•D3)
EIT4:
8 Hz interrupt mask register (FFEFH•D0)
EIT5:
4 Hz interrupt mask register (FFEFH•D1)
EIT6:
2 Hz interrupt mask register (FFEFH•D2)
EIT7:
1 Hz interrupt mask register (FFEFH•D3)
These registers are used to select whether to mask the clock timer interrupt.
When "1" is written: Enabled
When "0" is written: Masked
Reading: Valid
The interrupt mask registers (EIT0, EIT1, EIT2, EIT3, EIT4, EIT5, EIT6, EIT7) are used to select whether to
mask the interrupt to the separate frequencies (128 Hz, 64 Hz, 32 Hz, 16 Hz, 8 Hz, 4 Hz, 2 Hz, 1 Hz).
At initial reset, these registers are set to "0".
SIC63616-(Rev. 1.0) NO. P82
3240-0412
Advertisement
Table of Contents
