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Table 4.10.4.1 Mode settings and configurations of serial interface terminals
ESIF
SMOD
ENCS
1
1
1
1
1
*
1
1
0
1
1
*
1
1
0
1
0
1
1
0
1
1
0
0
1
0
0
1
0
1
1
0
1
0
*
*
4.10.5 Setting synchronous clock
Controlling clock manager
When the serial interface is used in master mode, it uses the internal clock supplied from the clock
manager as the synchronous clock for serial transfer. The clock manager generates six serial interface
clocks by dividing the OSC1 or OSC3 clock. The synchronous clock used in master mode can be selected
from seven types (the above six clocks and the programmable timer 1 output clock). Use the SIFCKS0–
SIFCKS2 register to select one of them as shown in Table 4.10.5.1.
When programmable timer 1 is selected, the programmable timer 1 underflow signal is divided by 2 be-
fore it is used as the synchronous clock. In this case, the programmable timer must be controlled before
operating the serial interface. Refer to Section 4.9, "Programmable Timer" for controlling the program-
mable timer.
Fix SIFCKS0–SIFCKS2 at "000B" in slave mode.
At initial reset, "internal clock Off (slave mode)" is selected.
Selecting the synchronous clock format
The format (polarity and phase) of the synchronous clock for the serial interface can be configured using
the SCPS0–SCPS1 register.
At initial reset, the clock polarity is set to positive and the phase is set to the rising edge.
See Figure 4.10.6.2 for the data transfer timings by the synchronous clock format selected.
ESREADY
ESOUT
1
*
Master mode
0
1
1
1
0
0
1
0
1
1
Slave mode
1
0
*
1
*
0
0
1
SPI slave mode
0
0
*
*
Serial I/F not used
Table 4.10.5.1 Serial interface clock frequencies
SIFCKS2
SIFCKS1
SIFCKS0
1
1
1
1
1
0
1
0
0
1
0
1
0
0
0
0
f
: OSC1 oscillation frequency. ( ) indicates the frequency when f
OSC1
f
: OSC3 oscillation frequency
OSC3
∗ The maximum clock frequency is limited to 1 MHz.
Table 4.10.5.2 Configuration of synchronous clock format
SCPS1
SCPS0
1
1
1
0
0
1
0
0
Mode
P20 terminal
SCLK (O)
SCLK (O)
SCLK (O)
SCLK (O)
SCLK (I)
SCLK (I)
SCLK (I)
SCLK (I)
SCLK (I)
SCLK (I)
P20 (I/O)
SIF clock (master mode)
1
f
/ 4 *
OSC3
0
f
/ 2 *
OSC3
1
f
/ 1 *
OSC3
0
Programmable timer 1 *
1
f
/ 4 (8 kHz)
OSC1
0
f
/ 2 (16 kHz)
OSC1
1
f
/ 1 (32 kHz)
OSC1
0
Off (slave mode) *
Polarity
Phase
Negative (SCLK)
Rising edge (
Negative (SCLK)
Falling edge (
Positive (SCLK)
Falling edge (
Positive (SCLK)
Rising edge (
SIC63616-(Rev. 1.0) NO. P124
P21 terminal
P22 terminal
P23 terminal
Prohibited
SOUT (O)
SIN (I)
SOUT (O)
SIN (I)
P21 (I/O)
SIN (I)
P21 (I/O)
SIN (I)
SOUT (O)
SIN (I)
P21 (I/O)
SIN (I)
SOUT (O)
SIN (I)
P21 (I/O)
SIN (I)
SOUT (O)
SIN (I)
P21 (I/O)
SIN (I)
P21 (I/O)
P22 (I/O)
= 32 kHz.
OSC1
)
)
)
)
P23 (I/O)
P23 (I/O)
P23 (I/O)
P23 (I/O)
SRDY (O)
SRDY (O)
P23 (I/O)
P23 (I/O)
SS (I)
SS (I)
P23 (I/O)
3240-0412
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