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4.12 Integer Multiplier
4.12.1 Configuration of integer multiplier
The S1C63616 has a built-in unsigned-integer multiplier. This multiplier performs 8 bits × 8 bits of
multiplication or 16 bits ÷ 8 bits of division and returns the results and three flag states.
Figure 4.12.1.1 shows the configuration of the integer multiplier.
Clock
manager
System clock
4.12.2 Controlling clock manager
The integer multiplier operates with the clock supplied by the clock manager (CPU operating clock selected
by OSCC and CLKCHG). Before the integer multiplier can be run, write "1" to the MDCKE register to
supply the operating clock to the integer multiplier.
If it is not necessary to run the integer multiplier, stop the clock supply by setting MDCKE to "0" to reduce
current consumption.
4.12.3 Multiplication mode
To perform a multiplication, set the multiplier to the source register (SR) and the multiplicand to the low-
order 8 bits (DRL) of the destination register, then write "0" to the calculation mode select register (CALMD).
The multiplication takes 10 CPU clock cycles from writing "0" to CALMD until the 16-bit product is loaded
into the destination register (DRH and DRL). At the same time the result is loaded, the operation flags (NF,
VF and ZF) are updated.
The following shows the conditions that change the operation flag states and examples of multiplication.
N flag: Set when the MSB of DRH is "1" and reset when it is "0".
V flag: Always reset after a multiplication.
Z flag: Set when the 16-bit value in DRH/DRL is 0000H and reset when it is not 0000H.
<Examples of multiplication>
DRL (multiplicand)
SR (multiplier) DRH/DRL (product) NF
00H
64H
C8H
C8H
Destination register
High-order byte (DRH)
Low-order byte (DRL)
Temporary
register A
Fig. 4.12.1.1 Configuration of the integer multiplier
Table 4.12.2.1 Controlling integer multiplier clock
MDCKE
1
When CLKCHG = "0":
When OSCC = 1", CLKCHG = "1": f
0
64H
0000H
58H
2260H
58H
44C0H
A5H
80E8H
Data bus
Source register
(SR)
Temporary
register B
Adder
Flag
(NF/VF/ZF)
Integer multiplier clock
f
OSC1
OSC3
Off
VF
ZF
0
0
1
0
0
0
0
0
0
1
0
0
SIC63616-(Rev. 1.0) NO. P143
Operation
control
(CALMD)
(32 kHz)
3240-0412
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