Epson S1C63616 Technical Manual page 121

PLPUL_A: Timer 0 pulse polarity select register (FF80H•D0)
PLPUL_B: Timer 2 pulse polarity select register (FF90H•D0)
PLPUL_C: Timer 4 pulse polarity select register (FFA0H•D0)
PLPUL_D: Timer 6 pulse polarity select register (FFB0H•D0)
Selects the count pulse polarity in the event counter mode.
When "1" is written: Rising edge
When "0" is written: Falling edge
Reading: Valid
The count timing in the event counter mode is selected from either the falling edge of the external clock
input to the P12, P41, P42 and P43 I/O port terminals or the rising edge. When "0" is written to these
registers, the falling edge is selected and when "1" is written, the rising edge is selected.
These registers are effective only when the timer is used in the event counter mode.
At initial reset, these registers are set to "0".
FCSEL_A: Timer 0 function select register (FF80H•D1)
FCSEL_B: Timer 2 function select register (FF90H•D1)
FCSEL_C: Timer 4 function select register (FFA0H•D1)
FCSEL_D: Timer 6 function select register (FFB0H•D1)
Selects whether the noise rejector of the clock input circuit will be used or not in the event counter mode.
When "1" is written: With noise rejector
When "0" is written: Without noise rejector
Reading: Valid
When "1" is written to these registers, the noise rejector is used and counting is done by an external clock
(input from P12, P41, P42 or P43) with 0.98 msec* or more pulse width. The noise rejector allows the coun-
ter to input the clock at the second falling edge of the internal 2,048 Hz* signal after changing the input
level of the I/O port terminal. Consequently, the pulse width of noise that can reliably be rejected is 0.48
msec* or less.
( ∗ : f = 32.768 kHz)
OSC1
When "0" is written to these registers, the noise rejector is not used and the counting is done directly by an
external clock input to the P12, P41, P42 or P43 I/O port terminal.
This registers are effective only when the timer is used in the event counter mode.
At initial reset, these registers are set to "0".
EVCNT_A: Timer 0 counter mode select register (FF80H•D2)
EVCNT_B: Timer 2 counter mode select register (FF90H•D2)
EVCNT_C: Timer 4 counter mode select register (FFA0H•D2)
EVCNT_D: Timer 6 counter mode select register (FFB0H•D2)
Selects the counter mode for each timer.
When "1" is written: Event counter mode
When "0" is written: Timer mode
Reading: Valid
The counter modes for Timers 0, 2, 4 and 6 are selected from either the event counter mode or timer mode.
When "1" is written to these registers, event counter mode is selected. In this mode, Timers 0, 2, 4 and 6
count the external clock input from the P12, P41, P42 and P43 I/O ports, respectively.
When "0" is written, timer mode is selected. In this mode, the timer count the internal clock selected by the
PTPS register.
This selection is effective even when these timer is used in 16-bit timer mode.
At initial reset, these registers are set to "0".
SIC63616-(Rev. 1.0) NO. P114
3240-0412