Epson S1C63616 Technical Manual page 184

Programmable timer
(1) When reading counter data, be sure to read the low-order 4 bits (PTDx0–PTDx3) first. The high-order
4 bits (PTDx4–PTDx7) are latched when the low-order 4 bits are read and they are held until the next
reading of the low-order 4 bits. In 16-bit timer mode, the high-order 12 bits are held by reading the low-
order 4 bits, be sure to read the low-order 4 bits first.
When the CPU is running with the OSC1 clock and the programmable timer is running with the OSC3
clock, stop the timer before reading the counter data to read the proper data.
(2) The programmable timer actually enters RUN/STOP status in synchronization with the falling edge of
the input clock after writing to the PTRUNx register. Consequently, when "0" is written to the PTRUNx
register, the timer enters STOP status at the point where the counter is decremented (-1). The PTRUNx
register maintains "1" for reading until the timer actually stops.
In event counter mode, the timer starts counting at the first event clock.
Fig. 5.2.2 Timing chart for RUN/STOP control (event counter mode)
(3) Since the TOUT_A signal is generated asynchronously from the PTOUT_A register, a hazard within 1/2
cycle is generated when the signal is turned on and off by setting the register.
(4) When the OSC3 oscillation clock is selected for the clock source, it is necessary to turn the OSC3 oscilla-
tion ON, prior to using the programmable timer. However the OSC3 oscillation circuit requires a time
at least 5 msec from turning the circuit ON until the oscillation stabilizes. Therefore, allow an adequate
interval from turning the OSC3 oscillation circuit ON to starting the programmable timer. Refer to Sec-
tion 4.4, "Oscillation Circuit", for the control and notes of the OSC3 oscillation circuit.
At initial reset, the OSC3 oscillation circuit is set in the off state.
(5) For the reason below, pay attention to the reload data write timing when changing the interval of the
programmable timer interrupts while the programmable timer is running.
The programmable timer counts down at the falling edge of the input clock and at the same time it gen-
erates an interrupt if the counter underflows. Then it starts loading the reload data to the counter and
the counter data is determined at the next rising edge of the input clock (period shown in as ➀ in the
figure).
Count clock
Counter data
(continuous mode)
Count clock
PTRUNx (RD)
"1" (RUN)
PTRUNx (WR)
PTDx0–PTDx7 42H
Fig. 5.2.1 Timing chart for RUN/STOP control (timer mode)
Count clock
PTRUNx (RD)
"1" (RUN)
PTRUNx (WR)
PTDx0–PTDx7 42H 41H 40H 3FH 3EH
03H 02H 01H
Underflow (interrupt is generated)
Fig. 5.2.3 Reload timing for programmable timer
"0" (STOP)
writing writing
41H 40H 3FH 3EH
"0" (STOP)
writing writing
➀
00H 25H 24H
Counter data is determined by reloading.
SIC63616-(Rev. 1.0) NO. P176
3DH
3DH
(Reload data = 25H)
3240-0412