Epson S1C63616 Technical Manual page 124

SIC63616-(Rev. 1.0) NO. P117
The PTRSTx registers are all effective even in 16-bit timer mode, and reload data must be preset to both the
high-order timer (Timer 1/3/5/7) and the low-order timer (Timer 0/2/4/6) separately.
Since these bits are exclusively for writing, always set to "0" during reading.
RLD00–RLD07: Timer 0 reload data register (FF84H, FF85H)
RLD10–RLD17: Timer 1 reload data register (FF86H, FF87H)
RLD20–RLD27: Timer 2 reload data register (FF94H, FF95H)
RLD30–RLD37: Timer 3 reload data register (FF96H, FF97H)
RLD40–RLD47: Timer 4 reload data register (FFA4H, FFA5H)
RLD50–RLD57: Timer 5 reload data register (FFA6H, FFA7H)
RLD60–RLD67: Timer 6 reload data register (FFB4H, FFB5H)
RLD70–RLD77: Timer 7 reload data register (FFB6H, FFB7H)
Sets the initial value for the counter.
The reload data written in these registers are loaded to the respective counters. The counter counts down
using the data as the initial value for counting.
Reload data is loaded to the counter when the counter is reset by writing "1" to the PTRSTx register, or
when counter underflow occurs.
At initial reset, these registers are set to "00H".
PTD00–PTD07: Timer 0 counter data (FF88H, FF89H)
PTD10–PTD17: Timer 1 counter data (FF8AH, FF8BH)
PTD20–PTD27: Timer 2 counter data (FF98H, FF99H)
PTD30–PTD37: Timer 3 counter data (FF9AH, FF9BH)
PTD40–PTD47: Timer 4 counter data (FFA8H, FFA9H)
PTD50–PTD57: Timer 5 counter data (FFAAH, FFABH)
PTD60–PTD67: Timer 6 counter data (FFB8H, FFB9H)
PTD70–PTD77: Timer 7 counter data (FFBAH, FFBBH)
Count data in the programmable timer can be read from these latches.
The low-order 4 bits of the count data in Timer x can be read from PTDx0–PTDx3, and the high-order data
can be read from PTDx4–PTDx7. Since the high-order 4 bits are held by reading the low-order 4 bits, be sure
to read the low-order 4 bits first. In 16-bit timer mode, the high-order 12 bits are held by reading the low-
order 4 bits, be sure to read the low-order 4 bits first.
Since these latches are exclusively for reading, the writing operation is invalid.
At initial reset, these counter data are set to "00H".
CD00–CD07: Timer 0 compare data register (FF8CH, FF8DH)
CD10–CD17: Timer 1 compare data register (FF8EH, FF8FH)
CD20–CD27: Timer 2 compare data register (FF9CH, FF9DH)
CD30–CD37: Timer 3 compare data register (FF9EH, FF9FH)
CD40–CD47: Timer 4 compare data register (FFACH, FFADH)
CD50–CD57: Timer 5 compare data register (FFAEH, FFAFH)
CD60–CD67: Timer 6 compare data register (FFBCH, FFBDH)
CD70–CD77: Timer 7 compare data register (FFBEH, FFBFH)
Sets the compare data for PWM output.
When the timer is set to PWM mode, the compare data set in this register is compared with the counter data
and outputs the compare match signal if they are matched. The compare match signal is used for generating
an interrupt and controlling the duty ratio of the PWM waveform.
At initial reset, these registers are set to "00H".
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