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III-2 PRESCALER
Configuration of Prescaler
The prescaler divides the source clock (OSC3/PLL output clock or OSC1 clock) to generate the clocks for the internal
peripheral circuits. The prescaler division ratio can be selected for each peripheral circuit in a program. A clock
control circuit to control the clock supply to each peripheral circuit is also included.
The following are the peripheral circuits that use the output clock:
• 16-bit programmable timers 5 to 0 (and watchdog timer)
• 8-bit programmable timers 5 to 0 (and serial interface)
• A/D converter
Figure 2.1 shows the configuration of the prescaler.
For details on control of each peripheral circuit, refer to each corresponding section in this manual.
PSCON
OSC3 or
PLL output clock
Selector
OSC1 clock
Source Clock
The source clock for the prescaler can be selected using PSCDT0 (D0) / Prescaer clock select register (0x40181).
When PSCDT0 = "0", the OSC3 clock (when the PLL is not used) or the PLL output clock (when the PLL is used) is
selected.
When PSCDT0 = "1", the OSC1 clock (typ. 32 kHz) is selected.
At initial reset, the OSC3/PLL output clock is selected.
Note: For the prescaler clock, the clock source same as the CPU operating clock must be selected.
For details on how to control the oscillation circuit and CPU operating clock, refer to "CLG (Clock Generator)".
At initial reset, the OSC3 clock is selected.
The source clock is supplied to the prescaler by writing "1" to PSCON (D5) / Power control register (0x40180). At
initial reset, PSCON is set to "1", so the prescaler is in an operating state. If all of the previously mentioned
peripheral circuits can be stopped, and the circuits that use the clock (the source clock) supplied to the prescaler (that
is, the 16-bit programmable timers (watchdog timer), 8-bit programmable timers (DRAM refresh), the A/D
converter, the serial interface, and the ports) can be stopped as well, stop the prescaler by setting PSCON to "0" to
reduce current consumption. Note that stopping the prescaler (by setting PSCON to "0") stops the clock (the source
clock) supplied to the prescaler.
S1C33210 FUNCTION PART
1/1
1/2
1/4
Division ratio
select register
Prescaler
output control
Figure 2.1 Configuration of Prescaler and Clock Control Circuit
III PERIPHERAL BLOCK: PRESCALER
1/8
1/16
1/32
1/64
1/128 1/256 1/512 1/1024 1/2048 1/4096
Selector
Control register
EPSON
16-bit programmable timer 5–0
8-bit programmable timer 3–0
A/D converter
B-III-2-1
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