Chapter 3 Cpu, Rom, Ram - Epson S1C63616 Technical Manual

3 Cpu, roM, raM
Chapter
3.1 CPU
The S1C63616 has a 4-bit core CPU S1C63000 built-in as its CPU part.
Refer to the "S1C63000 Core CPU Manual" for the S1C63000.
3.2 Code ROM
The built-in code ROM is a mask ROM for loading programs, and has a capacity of 16,384 words × 13
bits. The core CPU can linearly access the program space up to step FFFFH from step 0000H, however, the
program area of the S1C63616 is step 0000H to step 3FFFH. The program start address after initial reset is
assigned to step 0110H. The non-maskable interrupt (NMI) vector and hardware interrupt vectors are al-
located to step 0100H and steps 0101H–010FH, respectively.
0000H
Code ROM
3FFFH
4000H
Unused area
FFFFH
13 bits
3.3 RAM
The RAM is a data memory for storing various kinds of data, and has a capacity of 2,048 words × 4 bits. The
RAM area is assigned to addresses 0000H to 07FFH on the data memory map. Addresses 0100H to 01FFH
are 4-bit/16-bit data accessible areas and in other areas it is only possible to access 4-bit data. When pro-
gramming, keep the following points in mind.
(1) Part of the RAM area is used as a stack area for subroutine call and register evacuation, so pay atten-
tion not to overlap the data area and stack area.
(2) The S1C63000 core CPU handles the stack using the stack pointer for 4-bit data (SP2) and the stack
pointer for 16-bit data (SP1).
16-bit data are accessed in stack handling by SP1, therefore, this stack area should be allocated to
the area where 4-bit/16-bit access is possible (0100H to 01FFH). The stack pointers SP1 and SP2
change cyclically within their respective range: the range of SP1 is 0000H to 07FFH and the range of
SP2 is 0000H to 00FFH. Therefore, pay attention to the SP1 value because it may be set to 0200H or
more exceeding the 4-bit/16-bit accessible range in the S1C63616 or it may be set to 00FFH or less.
Memory accesses except for stack operations by SP1 are 4-bit data access.
After initial reset, all the interrupts including NMI are masked until both the stack pointers SP1 and
SP2 are set by software. Further, if either SP1 or SP2 is re-set when both are set already, the interrupts
including NMI are masked again until the other is re-set. Therefore, the settings of SP1 and SP2 must
be done as a pair.
0000H
S1C63616
0100H
program area
0101H
0110H
S1C63000 core CPU
program space
Fig. 3.2.1 Configuration of code ROM
Program area
NMI vector
Hardware
interrupt vectors
Program start address
Program area
010AH
010BH
010CH
010DH
010EH
010FH
SIC63616-(Rev. 1.0) NO. P14
0100H Watchdog timer
0101H R/f converter
0102H Programmable timer 0
0103H Programmable timer 1
0104H Programmable timer 2
0105H Programmable timer 3
0106H Programmable timer 4
0107H Programmable timer 5
0108H Programmable timer 6
0109H Programmable timer 7
Serial interface
Key input interrupt (P1)
Key input interrupt (P4)
Stopwatch
Clock timer (128/64/32/16 Hz)
Clock timer (8/4/2/1 Hz)
3240-0412