Interrupt And Halt/Sleep - Epson S1C63616 Technical Manual

4.15 Interrupt and HALT/SLEEP

<Interrupt types>
The S1C63616 provides the following interrupt functions.
External interrupt: • Key input interrupt
Internal interrupt: • Watchdog timer interrupt
• Programmable timer interrupt
• Serial interface interrupt
• Clock timer interrupt
• Stopwatch timer interrupt
• R/f converter interrupt
To authorize interrupt, the interrupt flag must be set to "1" (EI) and the necessary related interrupt mask
registers must be set to "1" (enable).
When an interrupt occurs the interrupt flag is automatically reset to "0" (DI), and interrupts after that are
inhibited.
The watchdog timer interrupt is an NMI (non-maskable interrupt), therefore, the interrupt is generated
regardless of the interrupt flag setting. Also the interrupt mask register is not provided. However, it is
possible to not generate NMI since software can stop the watchdog timer operation.
Figure 4.15.1 shows the configuration of the interrupt circuit.
Note: After an initial reset, all the interrupts including NMI are masked until both the stack pointers SP1
and SP2 are set with the software. Be sure to set the SP1 and SP2 in the initialize routine.
Further, when re-setting the stack pointer, the SP1 and SP2 must be set as a pair. When one of them
is set, all the interrupts including NMI are masked and interrupts cannot be accepted until the other
one is set.
<HALT/SLEEP>
The S1C63616 has the HALT and SLEEP functions that considerably reduce current consumption when it is
not necessary.
The CPU enters HALT status when the HALT instruction is executed. In HALT status, the operation of the
CPU is stopped. However, timers continue counting since the oscillation circuit operates. Reactivating the
CPU from HALT status is done by generating a hardware interrupt request including NMI.
When the CPU enters SLEEP status as the result of the SLP instruction, the CPU stops its operation and
the OSC1 and OSC3 oscillation circuits are also stop. Therefore, the power supply voltage booster/halver
cannot generate V in SLEEP mode. If it is used V
D2
necessary to switch V
DD
CPU wakes up, be sure to run the CPU with the OSC1 clock before setting the CPU in the SLEEP mode.
Reactivating from SLEEP status can only be done by generation of a key input interrupt request from a P1x
or P4x port.
Therefore, set and confirm the P1(4)x input level, the flag and the registers for the P1(4)x port, the CPU
clock, and the power control according to the following procedures to be used to enter/cancel SLEEP status
before executing the SLP instruction surely.
1. LCD system voltage regulator power source switch register VCSEL="0"
Power supply voltage booster/halver boost mode On/Off register DBON="0"
(LCD system voltage regulator is driven with V
2. CPU system clock switching register CLKCHG = "0" (OSC1 CPU clock is selected)
3. Interrupt selection register SIPxx = "1" (the Pxx input port interrupt is selected)
4. Interrupt mask register EIKxx = "1" (the Pxx input port interrupt is enabled)
before executing the SLP instruction. And to prevent improper operation after the
(8 systems)
(NMI, 1 system)
(16 systems)
(1 system)
(8 systems)
(4 systems)
(3 systems)
to drive the LCD system voltage regulator, it is
D2
)
DD
SIC63616-(Rev. 1.0) NO. P163
3240-0412