Table of Contents
Advertisement
Register
Address
D3
D2
D1
CLKCHG OSCC
FF00H
R/W
0
0
WDEN WDRST
FF01H
R
R/W
VDSEL VCSEL HLON
FF02H
R/W
VCHLMOD VDHLMOD General LPWR
FF03H
R/W
SVDS3 SVDS2 SVDS1 SVDS0
FF04H
R/W
0
0
SVDDT SVDON
FF05H
R
FOUT3 FOUT2 FOUT1 FOUT0
FF10H
R/W
NRSP11 NRSP10 NRSP01 NRSP00
FF11H
R/W
FLCKS1 FLCKS0 VCCKS1 VCCKS0
FF12H
R/W
General SIFCKS2 SIFCKS1 SIFCKS0
FF14H
R/W
General RFCKS2 RFCKS1 RFCKS0
FF15H
R/W
MDCKE SGCKE SWCKE RTCKE
FF16H
R/W
Remarks
∗ 1
Initial value at initial reset
∗ 2
Not set in the circuit
∗ 3
Constantly "0" when being read
Table 4.1.1 (a) I/O memory map (FF00H-FF16H)
∗1
D0
Name Init
CLKCHG
0
0
0
OSCC
0
∗3
∗2
0
–
R
∗3
∗2
0
–
∗3
∗2
0
–
∗3
∗2
0
–
WDEN
1
W
∗3
WDRST
Reset
VDSEL
0
DBON
VCSEL
0
HLON
0
DBON
0
VCHLMOD
0
VDHLMOD
0
General
0
LPWR
0
SVDS3
0
SVDS2
0
SVDS1
0
SVDS0
0
∗3
∗2
0
–
∗3
∗2
0
–
SVDDT
0
R/W
SVDON
0
FOUT3
0
FOUT2
0
FOUT1
0
FOUT0
0
NRSP11
0
NRSP10
0
NRSP01
0
NRSP00
0
FLCKS1
0
FLCKS0
0
VCCKS1
0
VCCKS0
0
General
0
SIFCKS2
0
SIFCKS1
0
SIFCKS0
0
General
0
RFCKS2
0
RFCKS1
0
RFCKS0
0
MDCKE
0
SGCKE
0
SWCKE
0
RTCKE
0
1
0
OSC3
OSC1
CPU clock switch
On
Off
OSC3 oscillation On/Off
Unused
Unused
Unused
Unused
Enable
Disable
Watchdog timer enable
Reset
Invalid
Watchdog timer reset (writing)
1
0
General-purpose register
V
V
Power source select for LCD system voltage regulator
D2
DD
On
Off
Power voltage booster/halver halving mode On/Off
On
Off
Power voltage booster/halver boost mode On/Off
On
Off
Heavy load protection mode On/Off for LCD system voltage regulator
On
Off
Heavy load protection mode On/Off for internal voltage regulator
1
0
General-purpose register
On
Off
LCD system voltage regulator On/Off
SVD criteria voltage setting
[SVDS3–0]
Voltage (V)
[SVDS3–0]
Voltage (V)
Unused
Unused
Low
Normal
SVD evaluation data
On
Off
SVD circuit On/Off
FOUT frequency selection
[FOUT3–0]
Frequency
Off
[FOUT3–0]
Frequency
[FOUT3–0]
Frequency
f
Key input interrupt noise reject frequency selection
[NRSP11, 10] (P40–P43)
Frequency
[NRSP01, 00] (P10–P13)
Frequency
Frame
frequency
selection
VC boost
frequency
selection
1
0
General-purpose register
Serial I/F
clock frequency
selection
1
0
General-purpose register
R/f converter
clock frequency
selection
Enable
Disable
Integer multiplier clock enable
Enable
Disable
Sound generator clock enable
Enable
Disable
Stopwatch timer clock enable
Enable
Disable
Clock timer clock enable
SIC63616-(Rev. 1.0) NO. P17
Comment
0
1
2
3
4
1.6
1.8
1.9
2.0
2.1
8
9
10
11
12
2.5
2.6
2.7
2.8
2.9
0
1
2
3
f
/256
f
/64
f
/32
OSC1
OSC1
OSC1
6
7
8
f
/2
f
f
/256
f
OSC1
OSC1
OSC3
OSC3
11
12
13
14
/16
f
/8
f
/4
f
OSC3
OSC3
OSC3
OSC3
0
1
Off
f
/16
f
OSC1
OSC1
0
1
Off
f
/16
f
OSC1
OSC1
[FLCKS1, 0]
0
1
32 Hz
24 Hz
Frequency
[VCCKS1, 0]
0
1
Frequency
Off
2 kHz
[SIFCKS2–0]
0
1
Frequency
Off/External
f
OSC1
[SIFCKS2–0]
4
5
Frequency
PT1
f
OSC3
[RFCKS2–0]
0
1
Frequency
Off
f
OSC1
[RFCKS2–0]
4
5
Frequency
PT1
f
OSC3
5
6
7
2.2
2.3
2.4
13
14
15
3.0
3.1
3.2
4
5
f
/16
f
/4
OSC1
OSC1
9
10
f
/32
/64
OSC3
15
/2
f
OSC3
2
3
/64
f
/256
OSC1
2
3
/64
f
/256
OSC1
2
3
16 Hz
8 Hz
2, 3
Prohibited
2
3
f
/2
f
/4
OSC1
OSC1
6
7
f
/2
f
/4
OSC3
OSC3
2
3
f
/2
f
/4
OSC1
OSC1
6
7
f
/2
f
/4
OSC3
OSC3
3240-0412
Advertisement
Table of Contents
