Epson S1C63616 Technical Manual page 137

SIFCKS0–SIFCKS2: Serial interface clock frequency select register (FF14H•D0–D2)
Selects the synchronous clock frequency in master mode.
When programmable timer 1 is selected, the programmable timer 1 underflow signal is divided by 2 before
it is used as the synchronous clock. In this case, the programmable timer must be controlled before operating
the serial interface. Refer to Section 4.9, "Programmable Timer" for controlling the programmable timer.
Fix at "000B" in slave mode.
At initial reset, this register is set to "000B".
PUL20: SCLK (P20) pull-down control register (FF2AH•D0)
PUL22: SIN( P22) pull-down control register (FF2AH•D2)
PUL23: SS (P23) pull-down control register (FF2AH•D3)
Enables the pull-down of the SIN, SCLK (in slave mode) and S
When "1" is written: Pull-down On
When "0" is written: Pull-down Off
Reading: Valid
Enables or disables the pull-down resistors built into the SIN (P22), SCLK (P20) and S
(Pull-down resistor is only built in the port selected by mask option.)
The SCLK and SS pull-down resistors are effective only in slave mode or SPI slave mode. In master mode,
the PUL20 and PUL23 registers can be used as general purpose registers.
At initial reset, these registers are set to "1" and pull-down goes on.
SMT20: SCLK (P20) input interface level select register (FF2BH•D0)
SMT22: SIN (P22) input interface level select register (FF2BH•D2)
SMT23: SS (P23) input interface level select register (FF2BH•D3)
Selects the input interface level of the SIN, SCLK (in slave mode) and SS (in SPI slave mode) terminals.
When "1" is written: CMOS Schmitt level
When "0" is written: CMOS level
Reading: Valid
Sets the input interface level of the SIN (P22), SCLK (P20) and SS (P23) terminals.
The SCLK and SS input interface level settings are effective only in slave mode or SPI slave mode. In master
mode, the SMT20 and SMT23 registers can be used as general purpose registers.
At initial reset, these registers are set to "1" and the ports are configured with a CMOS Schmitt level input
interface.
Table 4.10.8.2 Serial interface clock frequencies
SIFCKS2 SIFCKS1 SIFCKS0
1 1
1 1
1 0
1 0
0 1
0 1
0 0
0 0
f : OSC1 oscillation frequency. ( ) indicates the frequency when f
OSC1
f : OSC3 oscillation frequency
OSC3
∗ The maximum clock frequency is limited to 1 MHz.
SIF clock (master mode)
1 f / 4 *
OSC3
0 f / 2 *
OSC3
1 f / 1 *
OSC3
0 Programmable timer 1 *
1 f / 4 (8 kHz)
OSC1
0 f / 2 (16 kHz)
OSC1
1 f / 1 (32 kHz)
OSC1
0 Off (slave mode) *
_____
S (in SPI slave mode) terminals.
SIC63616-(Rev. 1.0) NO. P130
= 32 kHz.
OSC1
_____
S (P23) terminals.
3240-0412