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Serial data input/output permutation
The S1C63616 allows the input/output permutation of serial data to be selected by the SDP register as
to either LSB first or MSB first. The block diagram showing input/output permutation in case of LSB
first and MSB first is provided in Figure 4.10.6.1. The SDP register should be set before setting data to
SD0–SD7.
SIN
SIN
SRDY signal
When the S1C63616 serial interface is used in the slave mode, the SRDY signal is used to indicate wheth-
er the internal serial interface is ready to transmit or receive data for the master side (external) serial
device. The SRDY signal is output from the SRDY (P23) terminal. When using the SRDY output in slave
mode, write "1" to the ENCS and ESREADY registers (this signal cannot be used in SPI slave mode).
Output timing of SRDY signal is as follows:
•
When positive polarity (SCPS1 = "0") is selected for the synchronous clock:
The SRDY signal goes "1" (high) when the S1C63616 serial interface is ready to transmit or receive data;
normally, it is at "0" (low).
The SRDY signal changes from "0" to "1" immediately after "1" is written to SCTRG and returns from "1"
to "0" when "1" is input to the SCLK (P20) terminal (i.e., when the serial input/output begins transmit-
ting or receiving data). Moreover, when high-order data is read from or written to SD4–SD7, the SRDY
signal returns to "0".
•
When negative polarity (SCPS1 = "1") is selected for the synchronous clock:
The SRDY signal goes "0" (low) when the S1C63616 serial interface is ready to transmit or receive data;
normally, it is at "1" (high).
The SRDY signal changes from "1" to "0" immediately after "1" is written to SCTRG and returns from "0"
to "1" when "0" is input to the SCLK (P20) terminal (i.e., when the serial input/output begins transmit-
ting or receiving data). Moreover, when high-order data is read from or written to SD4–SD7, the SRDY
signal returns to "1".
Address [FF5CH]
Address [FF5BH]
SD7 SD6 SD5 SD4
SD3 SD2 SD1 SD0
(LSB first)
Address [FF5BH]
Address [FF5CH]
SD0 SD1 SD2 SD3
SD4 SD5 SD6 SD7
(MSB first)
Fig. 4.10.6.1 Serial data input/output permutation
SIC63616-(Rev. 1.0) NO. P126
Output
SOUT
latch
Output
SOUT
latch
3240-0412
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