Setting Of Input Clock In Timer Mode - Epson S1C6P366 Technical Manual

2,048 Hz
K13 input
Counter
input clock
Counter data
The operation of the event counter mode is the same as the timer mode except it uses the K13 input as
the clock.
Refer to Section 4.9.2.1, "Setting of initial value and counting down" for basic operation and control.

4.9.2.3 Setting of input clock in timer mode

Timer 0 and timer 1 each include a prescaler. The prescalers generate the input clock for each timer by
dividing the source clock supplied from the OSC1 or OSC3 oscillation circuit.
The source clock (OSC1 or OSC3) and the division ratio of the prescaler can be selected with software for
timer 0 and timer 1 individually.
The set input clock is used for the count clock during operation in the timer mode. When the timer 0 is
used in the event counter mode, the following settings become invalid.
The input clock is set in the following sequence.
(1) Selection of source clock
Select the source clock input to each prescaler from either OSC1 or OSC3. This selection is done using
the source clock selection registers CKSEL0 (timer 0) and CKSEL1 (timer 1); when "0" is written to the
register, OSC1 is selected and when "1" is written, OSC3 is selected.
When the OSC3 oscillation clock is selected for the clock source, it is necessary to turn the OSC3
oscillation ON, prior to using the programmable timer. However the OSC3 oscillation circuit requires
a time interval of several msec to several 10 msec from turning the circuit ON until the oscillation
stabilizes. Therefore, allow an adequate interval from turning the OSC3 oscillation circuit ON to
starting the programmable timer. Refer to Section 4.3, "Oscillation Circuit", for the control and notes of
the OSC3 oscillation circuit.
At initial reset, the OSC3 oscillation circuit is set in the OFF state.
(2) Selection of prescaler division ratio
Select the division ratio for each prescaler from among 4 types. This selection is done using the
prescaler division ratio selection registers PTPS00/PTPS01 (timer 0) and PTPS10/PTPS11 (timer 1).
Table 4.9.2.3.1 shows the correspondence between the setting value and the division ratio.
By writing "1" to the register PTRUN0 (timer 0) or PTRUN1 (timer 1), the prescaler inputs the source
clock and outputs the clock divided by the selected division ratio. The counter starts counting down
by inputting the clock.
S1C6P366 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmble Timer)
n
When PLPOL register is set to "0"
Fig. 4.9.2.2.2 Count down timing with noise rejecter
Table 4.9.2.3.1 Selection of prescaler division ratio
PTPS11 PTPS10
PTPS01 PTPS00
1 1
1 0
0 1
0 0
EPSON
n-1 n-2
Prescaler division ratio
Source clock / 256
Source clock / 32
Source clock / 4
Source clock / 1
n-3
61