Table of Contents
Advertisement
4.10.3 Setting of input clock in timer mode
Timer 0 and timer 1 each include a prescaler. The prescalers generate the input clock for each timer by
dividing the source clock supplied from the OSC1 or OSC3 oscillation circuit.
The source clock (OSC1 or OSC3) and the division ratio of the prescaler can be selected with software for
timer 0 and timer 1 individually.
The input clock is set in the following sequence.
(1) Selection of source clock
Select the source clock input to each prescaler from either OSC1 or OSC3. This selection is done using
the source clock selection registers CKSEL0 (timer 0) and CKSEL1 (timer 1); when "0" is written to the
register, OSC1 is selected and when "1" is written, OSC3 is selected.
When the OSC3 oscillation clock is selected for the clock source, it is necessary to turn the OSC3
oscillation ON, prior to using the programmable timer. However the OSC3 oscillation circuit requires
a time at least 5 msec from turning the circuit ON until the oscillation stabilizes. Therefore, allow an
adequate interval from turning the OSC3 oscillation circuit ON to starting the programmable timer.
Refer to Section 4.3, "Oscillation Circuit", for the control and notes of the OSC3 oscillation circuit.
At initial reset, the OSC3 oscillation circuit is set in the OFF state.
(2) Selection of prescaler division ratio
Select the division ratio for each prescaler from among 4 types. This selection is done using the
prescaler division ratio selection registers PTPS00/PTPS01 (timer 0) and PTPS10/PTPS11 (timer 1).
Table 4.10.3.1 shows the correspondence between the setting value and the division ratio.
By writing "1" to the register PTRUN0 (timer 0) or PTRUN1 (timer 1), the prescaler inputs the source
clock and outputs the clock divided by the selected division ratio. The counter starts counting down
by inputting the clock.
4.10.4 Interrupt function
The programmable timer can generate an interrupt due to an underflow of the timer 0 and timer 1. See
Figure 4.10.2.1 for the interrupt timing.
An underflow of timer 0 and timer 1 sets the corresponding interrupt factor flag IPT0 (timer 0) or IPT1
(timer 1) to "1", and generates an interrupt. The interrupt can also be masked by setting the correspond-
ing interrupt mask register EIPT0 (timer 0) or EIPT1 (timer 1). However, the interrupt factor flag is set to
"1" by an underflow of the corresponding timer regardless of the interrupt mask register setting.
S1C63454 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
Table 4.10.3.1 Selection of prescaler division ratio
PTPS11
PTPS10
PTPS01
PTPS00
1
1
1
0
0
1
0
0
EPSON
Prescaler division ratio
Source clock / 256
Source clock / 32
Source clock / 4
Source clock / 1
61
Advertisement
Table of Contents
