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Philips Semiconductors
Table 91:
Bit
Symbol
Reset
Fig 39. SPI single master single slave configuration.
In
The SPI master can use any port pin (including P2.4/SS) to drive the SS pin.
Fig 40. SPI dual device configuration, where either can be a master or a slave.
Figure 40
can be a master or a slave. When no SPI operation is occurring, both can be configured
as masters (MSTR = 1) with SSIG cleared to 0 and P2.4 (SS) configured in
quasi-bidirectional mode. When a device initiates a transfer, it can configure P2.4 as an
output and drive it low, forcing a mode change in the other device (see
change on
User manual
SPI Data register (SPDAT - address E3h) bit allocation
7
6
MSB
0
0
master
8-BIT SHIFT
REGISTER
SPI CLOCK
GENERATOR
Figure
39, SSIG (SPCTL.7) for the slave is logic 0, and SS is used to select the slave.
master
8-BIT SHIFT
REGISTER
SPI CLOCK
GENERATOR
shows a case where two devices are connected to each other and either device
SS") to slave.
Rev. 03 — 7 June 2005
5
4
3
0
0
0
MISO
MOSI
SPICLK
PORT
MISO
MOSI
SPICLK
SS
UM10119
P89LPC938 User manual
2
1
0
LSB
0
0
0
slave
MISO
8-BIT SHIFT
MOSI
REGISTER
SPICLK
SS
002aaa901
slave
MISO
8-BIT SHIFT
MOSI
REGISTER
SPICLK
SPI CLOCK
SS
GENERATOR
002aaa902
Section 13.4 "Mode
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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