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Philips Semiconductors
2
12.3 I
The CPU can read and write this register. There are two bits are affected by hardware: the
SI bit and the STO bit. The SI bit is set by hardware and the STO bit is cleared by
hardware.
CRSEL determines the SCL source when the I
this bit is ignored and the bus will automatically synchronize with any clock frequency up
to 400 kHz from the master I
Timer 1 overflow rate divided by 2 for the I
by the user in 8 bit auto-reload mode (Mode 2).
Data rate of I
If f
3000 Kbit/sec.
When CRSEL = 0, the I
of I2SCLL and I2CSCLH register. The duty cycle does not need to be 50 %.
The STA bit is START flag. Setting this bit causes the I
and attempt transmitting a START condition or transmitting a repeated START condition
when it is already in master mode.
The STO bit is STOP flag. Setting this bit causes the I
condition in master mode, or recovering from an error condition in slave mode.
If the STA and STO are both set, then a STOP condition is transmitted to the I
in master mode, and transmits a START condition afterwards. If it is in slave mode, an
internal STOP condition will be generated, but it is not transmitted to the bus.
Table 76:
Bit
Symbol
Reset
Table 77:
Bit Symbol
0
1
2
User manual
C control register
2
C-bus = Timer overflow rate / 2 = PCLK / (2*(256-reload value)).
= 12 MHz, reload value is 0 to 255, so I
osc
2
C interface uses the internal clock generator based on the value
2
I
C Control register (I2CON - address D8h) bit allocation
7
6
-
I2EN
x
0
2
I
C Control register (I2CON - address D8h) bit description
Description
CRSEL
SCL clock selection. When set = 1, Timer 1 overflow generates SCL, when cleared
= 0, the internal SCL generator is used base on values of I2SCLH and I2SCLL.
-
reserved
AA
The Assert Acknowledge Flag. When set to 1, an acknowledge (low level to SDA)
will be returned during the acknowledge clock pulse on the SCL line on the
following situations:
(1)The 'own slave address' has been received. (2)The general call address has
been received while the general call bit (GC) in I2ADR is set. (3) A data byte has
been received while the I
byte has been received while the I
Mode. When cleared to 0, an not acknowledge (high level to SDA) will be returned
during the acknowledge clock pulse on the SCL line on the following situations: (1)
A data byte has been received while the I
Mode. (2) A data byte has been received while the I
Slave Receiver Mode.
Rev. 03 — 7 June 2005
2
C-bus is in master mode. In slave mode
2
C device. When CRSEL = 1, the I
2
C clock rate. Timer 1 should be programmed
2
C data rate range is 11.72 Kbit/sec to
5
4
3
STA
STO
SI
0
0
0
2
C interface is in the Master Receiver Mode. (4)A data
2
C interface is in the addressed Slave Receiver
2
UM10119
P89LPC938 User manual
2
C interface uses the
2
C interface to enter master mode
2
C interface to transmit a STOP
2
2
1
AA
-
0
x
C interface is in the Master Receiver
2
C interface is in the addressed
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
C-bus if it is
0
CRSEL
0
78 of 139
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