Table of Contents
Advertisement
Philips Semiconductors
The first byte transmitted contains the slave address of the receiving device (7 bits) and
the data direction bit. In this case, the data direction bit (R/W) will be logic 0 indicating a
write. Data is transmitted 8 bits at a time. After each byte is transmitted, an acknowledge
bit is received. START and STOP conditions are output to indicate the beginning and the
end of a serial transfer.
The I
send the START condition as soon as the bus is free. After the START condition is
transmitted, the SI bit is set, and the status code in I2STAT should be 08h. This status
code must be used to vector to an interrupt service routine where the user should load the
slave address to I2DAT (Data Register) and data direction bit (SLA+W). The SI bit must be
cleared before the data transfer can continue.
When the slave address and R/W bit have been transmitted and an acknowledgment bit
has been received, the SI bit is set again, and the possible status codes are 18h, 20h, or
38h for the master mode or 68h, 78h, or 0B0h if the slave mode was enabled (setting
AA = Logic 1). The appropriate action to be taken for each of these status codes is shown
in
Fig 32. Format in the Master Transmitter mode.
12.6.2 Master Receiver mode
In the Master Receiver Mode, data is received from a slave transmitter. The transfer
started in the same manner as in the Master Transmitter Mode. When the START
condition has been transmitted, the interrupt service routine must load the slave address
and the data direction bit to I
the data transfer can continue.
When the slave address and data direction bit have been transmitted and an acknowledge
bit has been received, the SI bit is set, and the Status Register will show the status code.
For master mode, the possible status codes are 40H, 48H, or 38H. For slave mode, the
possible status codes are 68H, 78H, or B0H. Refer to
User manual
2
C-bus will enter Master Transmitter Mode by setting the STA bit. The I
Table
83.
S
slave address
from Master to Slave
from Slave to Master
Rev. 03 — 7 June 2005
R/W
A
DATA
logic 0 = write
data transferred
logic 1 = read
(n Bytes + acknowledge)
A = acknowledge (SDA LOW)
A = not acknowledge (SDA HIGH)
S = START condition
P = STOP condition
2
C Data Register (I2DAT). The SI bit must be cleared before
UM10119
P89LPC938 User manual
2
C logic will
A
DATA
A/A
P
002aaa929
Table 85
for details.
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
81 of 139
Advertisement
Table of Contents
