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Philips Semiconductors
Table 35:
Timer/Counter Mode register (TMOD - address 89h) bit description
Bit Symbol
Description
4
T1M0
Mode Select for Timer 1. These bits are used with the T1M2 bit in the TAMOD register to determine the
Timer 1 mode (see
5
T1M1
6
T1C/T
Timer or Counter Selector for Timer 1. Cleared for Timer operation (input from CCLK). Set for Counter
operation (input from T1 input pin).
7
T1GATE Gating control for Timer 1. When set, Timer/Counter is enabled only while the INT1 pin is high and the TR1
control pin is set. When cleared, Timer 1 is enabled when the TR1 control bit is set.
Table 36:
Timer/Counter Auxiliary Mode register (TAMOD - address 8Fh) bit allocation
Bit
7
Symbol
--
Reset
x
Table 37:
Timer/Counter Auxiliary Mode register (TAMOD - address 8Fh) bit description
Bit Symbol
Description
0
T0M2
Mode Select for Timer 0. These bits are used with the T0M2 bit in the TAMOD register to determine the
Timer 0 mode (see
1:3 -
reserved
4
T1M2
Mode Select for Timer 1. These bits are used with the T1M2 bit in the TAMOD register to determine the
Timer 1 mode (see
The following timer modes are selected by timer mode bits TnM[2:0]:
000 — 8048 Timer 'TLn' serves as 5-bit prescaler. (Mode 0)
001 — 16-bit Timer/Counter 'THn' and 'TLn' are cascaded; there is no prescaler.(Mode 1)
010 — 8-bit auto-reload Timer/Counter. THn holds a value which is loaded into TLn when it overflows.
(Mode 2)
011 — Timer 0 is a dual 8-bit Timer/Counter in this mode. TL0 is an 8-bit Timer/Counter controlled by the
standard Timer 0 control bits. TH0 is an 8-bit timer only, controlled by the Timer 1 control bits (see text).
Timer 1 in this mode is stopped. (Mode 3)
100 — Reserved. User must not configure to this mode.
101 — Reserved. User must not configure to this mode.
110 — PWM mode (see
111 — Reserved. User must not configure to this mode.
5:7 -
reserved
8.1 Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit
Counter with a divide-by-32 prescaler.
In this mode, the Timer register is configured as a 13-bit register. As the count rolls over
from all 1s to all 0s, it sets the Timer interrupt flag TFn. The count input is enabled to the
Timer when TRn = 1 and either TnGATE = 0 or INTn = 1. (Setting TnGATE = 1 allows the
Timer to be controlled by external input INTn, to facilitate pulse width measurements).
TRn is a control bit in the Special Function Register TCON
in the TMOD register.
User manual
Table
37).
6
5
-
-
x
x
Table
37).
Table
37).
Section
8.5).
Rev. 03 — 7 June 2005
4
3
T1M2
-
0
x
Figure 15
shows Mode 0 operation.
UM10119
P89LPC938 User manual
...continued
2
1
-
-
x
x
(Table
39). The TnGATE bit is
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
0
T0M2
0
46 of 139
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