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Philips Semiconductors
11.9 Break detect
A break detect is reported in the status register (SSTAT). A break is detected when any 11
consecutive bits are sensed low. Since a break condition also satisfies the requirements
for a framing error, a break condition will also result in reporting a framing error. Once a
break condition has been detected, the UART will go into an idle state and remain in this
idle state until a stop bit has been received. The break detect can be used to reset the
device and force the device into ISP mode by setting the EBRR bit (AUXR1.6)
Table 65:
Bit
Symbol
Reset
Table 66:
Bit Symbol
0
1
2
3
4
5
6
7
Table 67:
SM0, SM1
00
01
10
11
User manual
Serial Port Control register (SCON - address 98h) bit allocation
7
6
SM0/FE
SM1
x
x
Serial Port Control register (SCON - address 98h) bit description
Description
RI
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or
approximately halfway through the stop bit time in Mode 1. For Mode 2 or Mode 3,
if SMOD0, it is set near the middle of the 9th data bit (bit 8). If SMOD0 = 1, it is set
near the middle of the stop bit (see SM2 - SCON.5 - for exceptions). Must be
cleared by software.
TI
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or
at the stop bit (see description of INTLO bit in SSTAT register) in the other modes.
Must be cleared by software.
RB8
The 9th data bit that was received in Modes 2 and 3. In Mode 1 (SM2 must be 0),
RB8 is the stop bit that was received. In Mode 0, RB8 is undefined.
TB8
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software
as desired.
REN
Enables serial reception. Set by software to enable reception. Clear by software to
disable reception.
SM2
Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or
3, if SM2 is set to 1, then Rl will not be activated if the received 9th data bit (RB8)
is 0. In Mode 0, SM2 should be 0. In Mode 1, SM2 must be 0.
SM1
With SM0 defines the serial port mode, see
SM0/FE
The use of this bit is determined by SMOD0 in the PCON register. If SMOD0 = 0,
this bit is read and written as SM0, which with SM1, defines the serial port mode. If
SMOD0 = 1, this bit is read and written as FE (Framing Error). FE is set by the
receiver when an invalid stop bit is detected. Once set, this bit cannot be cleared
by valid frames but is cleared by software. (Note: UART mode bits SM0 and SM1
should be programmed when SMOD0 is logic 0 - default mode on any reset.)
Serial Port modes
UART mode
Mode 0: shift register
Mode 1: 8-bit UART
Mode 2: 9-bit UART
Mode 3: 9-bit UART
Rev. 03 — 7 June 2005
5
4
3
SM2
REN
TB8
x
x
x
Table
UART baud rate
⁄
CCLK
(default mode on any reset)
16
Variable (see
⁄
CCLK
CCLK
or
32
Variable (see
UM10119
P89LPC938 User manual
2
1
0
RB8
TI
RI
x
0
0
67.
Table
62)
⁄
16
Table
62)
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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