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11.7 Updating the BRGR1 and BRGR0 SFRs
The baud rate SFRs, BRGR1 and BRGR0 must only be loaded when the Baud Rate
Generator is disabled (the BRGEN bit in the BRGCON register is logic 0). This avoids the
loading of an interim value to the baud rate generator. (CAUTION: If either BRGR0 or
BRGR1 is written when BRGEN = 1, the result is unpredictable.)
Table 62:
SCON.7
(SM0)
0
0
1
1
Table 63:
Bit
Symbol
Reset
Table 64:
Bit Symbol
0
1
2:7 -
Fig 26. Baud rate generation for UART (Modes 1, 3).
11.8 Framing error
A Framing error occurs when the stop bit is sensed as a logic 0. A Framing error is
reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6) is 1, framing
errors can be made available in SCON.7. If SMOD0 is 0, SCON.7 is SM0. It is
recommended that SM0 and SM1 (SCON[7:6]) are programmed when SMOD0 is logic 0.
User manual
UART baud rate generation
SCON.6
PCON.7
(SM1)
(SMOD1)
0
X
1
0
1
X
0
0
1
1
0
1
X
Baud Rate Generator Control register (BRGCON - address BDh) bit allocation
7
6
5
--
-
-
x
x
x
Baud Rate Generator Control register (BRGCON - address BDh) bit description
Description
BRGEN
Baud Rate Generator Enable. Enables the baud rate generator. BRGR1 and
BRGR0 can only be written when BRGEN = 0.
SBRGS
Select Baud Rate Generator as the source for baud rates to UART in modes 1 and
3 (see
Table 62
for details)
reserved
timer 1 overflow
(PCLK-based)
baud rate generator
(CCLK-based)
Rev. 03 — 7 June 2005
BRGCON.1
Receive/transmit baud rate for UART
(SBRGS)
⁄
CCLK
X
16
⁄
CCLK
0
(256−TH1)64
⁄
CCLK
0
(256−TH1)32
⁄
CCLK
1
((BRGR1, BRGR0)+16)
⁄
CCLK
X
32
⁄
CCLK
X
16
⁄
CCLK
0
(256−TH1)64
⁄
CCLK
0
(256−TH1)32
⁄
CCLK
1
((BRGR1, BRGR0)+16)
4
3
-
-
x
x
SMOD1 = 1
SBRGS = 0
÷2
SMOD1 = 0
SBRGS = 1
UM10119
P89LPC938 User manual
2
1
0
-
SBRGS
BRGEN
x
0
0
baud rate modes 1 and 3
002aaa897
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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