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Fig 41. SPI single master multiple slaves configuration.
In
by the corresponding SS signals. The SPI master can use any port pin (including
P2.4/SS) to drive the SS pins.
13.1 Configuring the SPI
Table 92
for the modes.
Table 92:
SPI master and slave selection
SPEN
SSIG
SS Pin MSTR
[1]
0
x
P2.4
x
1
0
0
0
1
0
1
0
1
0
0
1 (->
0)
User manual
master
8-BIT SHIFT
REGISTER
SPI CLOCK
GENERATOR
Figure
41, SSIG (SPCTL.7) bits for the slaves are logic 0, and the slaves are selected
shows configuration for the master/slave modes as well as usages and directions
Master
MISO
or Slave
Mode
[1]
SPI
P2.3
Disabled
Slave
output
Slave
Hi-Z
Slave
output
[2]
Rev. 03 — 7 June 2005
MISO
MOSI
SPICLK
port
port
MOSI
SPICLK Remarks
[1]
[1]
P2.2
P2.5
SPI disabled. P2.2, P2.3, P2.4, P2.5 are used
as port pins.
input
input
Selected as slave.
input
input
Not selected. MISO is high-impedance to avoid
bus contention.
input
input
P2.4/SS is configured as an input or
quasi-bidirectional pin. SSIG is 0. Selected
externally as slave if SS is selected and is
driven low. The MSTR bit will be cleared to
logic 0 when SS becomes low.
UM10119
P89LPC938 User manual
slave
MISO
8-BIT SHIFT
MOSI
REGISTER
SPICLK
SS
slave
MISO
8-BIT SHIFT
MOSI
REGISTER
SPICLK
SS
002aaa903
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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