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Philips Semiconductors
Fig 14. Block diagram of reset.
Table 32:
Reset Sources register (RSTSRC - address DFh) bit allocation
Bit
7
Symbol
-
[1]
Reset
x
[1]
The value shown is for a power-on reset. Other reset sources will set their corresponding bits.
Table 33:
Reset Sources register (RSTSRC - address DFh) bit description
Bit Symbol Description
0
R_EX
external reset Flag. When this bit is logic 1, it indicates external pin reset. Cleared by software by writing a
logic 0 to the bit or a Power-on reset. If RST is still asserted after the Power-on reset is over, R_EX will be set.
1
R_SF
software reset Flag. Cleared by software by writing a logic 0 to the bit or a Power-on reset
2
R_WD
Watchdog Timer reset flag. Cleared by software by writing a logic 0 to the bit or a Power-on reset.(NOTE:
UCFG1.7 must be = 1)
3
R_BK
break detect reset. If a break detect occurs and EBRR (AUXR1.6) is set to logic 1, a system reset will occur.
This bit is set to indicate that the system reset is caused by a break detect. Cleared by software by writing a
logic 0 to the bit or on a Power-on reset.
4
POF
Power-on Detect Flag. When Power-on Detect is activated, the POF flag is set to indicate an initial power-up
condition. The POF flag will remain set until cleared by software by writing a logic 0 to the bit. (Note: On a
Power-on reset, both BOF and this bit will be set while the other flag bits are cleared.)
5
BOF
Brownout Detect Flag. When Brownout Detect is activated, this bit is set. It will remain set until cleared by
software by writing a logic 0 to the bit. (Note: On a Power-on reset, both POF and this bit will be set while the
other flag bits are cleared.)
6:7 -
reserved
User manual
•
For any other reset, any previously set flag bits that have not been cleared will remain
set.
RPE (UCFG1.6)
RST pin
WDTE (UCFG1.7)
Watchdog timer reset
Software reset SRST (AUXR1.3)
Power-on detect
UART break detect
EBRR (AUXR1.6)
Brownout detect reset
BOPD (PCON.5)
6
5
-
BOF
x
1
Rev. 03 — 7 June 2005
4
3
POF
R_BK
1
0
UM10119
P89LPC938 User manual
chip reset
2
1
R_WD
R_SF
0
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
002aaa918
0
R_EX
0
44 of 139
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