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P89LPC907
Philips P89LPC907 Manuals
Manuals and User Guides for Philips P89LPC907. We have
1
Philips P89LPC907 manual available for free PDF download: User Manual
Philips P89LPC907 User Manual (110 pages)
8-bit microcontrollers with accelerated two-clock 80C51 core 1KB 3V Low-Power byte-eraseable Flash with 128 Byte RAM
Brand:
Philips
| Category:
Computer Hardware
| Size: 1.21 MB
Table of Contents
Table of Contents
2
1 General Description
7
Pin Configurations
7
Product Comparison
8
Pin Descriptions - P89LPC906
12
Pin Descriptions - P89LPC907
13
Pin Descriptions - P89LPC908
14
Special Function Registers
15
Special Function Registers Table - P89LPC906
15
Special Function Registers Table - P89LPC907
18
Special Function Registers Table - P89LPC908
21
Memory Organization
24
P89LPC906/907/908 Memory Map
24
2 Clocks
25
Enhanced CPU
25
Clock Definitions
25
CPU Clock (OSCCLK)
25
Low Speed Oscillator Option - P89LPC906
25
Medium Speed Oscillator Option - P89LPC906
25
High Speed Oscillator Option - P89LPC906
25
Oscillator Option Selection- P89LPC906
26
Clock Output - P89LPC906
26
On-Chip RC Oscillator Option
26
Duce Power Consumption. on Reset, CLKLP Is '0' Allowing Highest Performance Access. this Bit Can then be Set in Software if CCLK Is Running at 8Mhz or Slower
26
Watchdog Oscillator Option
26
Using the Crystal Oscillator - P89LPC906
26
External Clock Input Option - P89LPC906
27
CPU Clock (CCLK) Wakeup Delay
27
CPU Clock (CCLK) Modification: DIVM Register
27
On-Chip RC Oscillator TRIM Register
27
Low Power Select (P89LPC906)
28
Block Diagram of Oscillator Control - P89LPC906
28
Block Diagram of Oscillator Control- P89LPC907,P89LPC908
29
3 Interrupts
31
Interrupt Priority Structure
31
Interrupt Priority Level
31
Summary of Interrupts - P89LPC906
31
External Interrupt Inputs
32
External Interrupt Pin Glitch Suppression
32
Summary of Interrupts - P89LPC907,P89LPC908
32
Interrupt Sources, Enables, and Power down Wake-Up Sources - P89LPC906
33
Interrupts Sources, Enables, and Power down Wake-Up Sources - P89LPC907,P89LPC908
33
4 I/O Ports
35
Port Configurations
35
Quasi-Bidirectional Output Configuration
35
Number of I/O Pins Available
35
Port Output Configuration Settings
35
Open Drain Output Configuration
36
Quasi-Bidirectional Output
36
Open Drain Output
36
Input-Only Configuration
37
Push-Pull Output Configuration
37
Port 0 Analog Functions
37
Input Only
37
Push-Pull Output
37
Port Output Configuration - P89LPC906
38
Port Output Configuration - P89LPC907
38
Port Output Configuration - P89LPC908
38
Additional Port Features
38
5 Timers 0 and 1
41
Timer/Counter Mode Control Register (TMOD)
41
Mode 0
42
Mode 2
42
Mode 3
43
Mode 6 - P89LPC907
43
Timer/Counter Control Register (TCON)
43
Timer/Counter 0 or 1 in Mode 0 (13-Bit Counter)
44
Timer/Counter 0 or 1 in Mode 1 (16-Bit Counter)
44
Timer/Counter 0 or 1 in Mode 2 (8-Bit Auto-Reload)
44
Timer Overflow Toggle Output - P89LPC907
45
Timer/Counter 0 Mode 3 (Two 8-Bit Counters)
45
Timer/Counter 0 in Mode 6 (PWM Auto-Reload), P89LPC907
45
6 Real-Time Clock/System Timer
47
Real-Time Clock Source
47
Real-Time Clock/System Timer Block Diagram
48
Real-Time Clock/System Timer Clock Source - P89LPC906
48
Real-Time Clock/System Timer Clock Source - P89LPC907,P89LPC908
49
Changing RTCS1-0
50
Real-Time Clock Interrupt/Wake up
50
Reset Sources Affecting the Real-Time Clock
50
RTCCON Register
51
7 Power Monitoring Functions
53
Brownout Detection
53
Power-On Detection
54
Power Reduction Modes
54
Brownout Options
54
Power Reduction Modes
55
Power Control Register (PCON)
56
Power Control Register (PCONA)
57
8 Uart (P89Lpc907, P89Lpc908)
59
Mode 0
59
Mode 1
59
Mode 2
59
Mode 3
59
SFR Space
60
Baud Rate Generator and Selection
60
Updating the BRGR1 and BRGR0 Sfrs
60
SFR Locations for Uarts
60
Baud Rate Generation for UART
60
Framing Error
61
Break Detect
61
BRGCON Register
61
Baud Rate Generations for UART (Modes 1, 3)
61
Serial Port Control Register (SCON)
62
More about UART Mode 0
63
Serial Port Status Register (SSTAT)
63
More about UART Mode 1
64
Serial Port Mode 0 (Double Buffering Must be Disabled)
64
Serial Port Mode 1 (Only Single Transmit Buffering Case Is Shown)
64
More about UART Modes 2 and 3
65
Framing Error and RI in Modes 2 and 3 with SM2 = 1
65
Break Detect
65
Serial Port Mode 2 or 3 (Only Single Transmit Buffering Case Is Shown)
65
Double Buffering
66
Double Buffering in Different Modes
66
Transmit Interrupts with Double Buffering Enabled (Modes 1, 2 and 3)
66
The 9Th Bit (Bit 8) in Double Buffering (Modes 1, 2 and 3)
67
Transmission with and Without Double Buffering
67
Multiprocessor Communications
68
Automatic Address Recognition
68
9 Reset
71
Power-On Reset Code Execution
71
Block Diagram of Reset
71
Reset Sources Register
72
10 Analog Comparators
73
Comparator Configuration
73
Comparator Control Register (CMP1)
73
Internal Reference Voltage
74
Comparator Interrupt
74
Comparator and Power Reduction Modes
74
Comparator Input and Output Connections
74
Comparator Configurations
74
Comparator Configuration Example
75
11 Keypad Interrupt (KBI)
77
Keypad Pattern Register
77
Keypad Control Register
77
Keypad Interrupt Mask Register (KBM)
78
12 Watchdog Timer
79
Watchdog Function
79
Watchdog Timer Configuration
79
Feed Sequence
80
Watchdog Prescaler
80
Watchdog Timer Control Register
81
P89LPC906/907/908 Watchdog Timeout Values
82
Watchdog Timer in Timer Mode
83
Watchdog Timer in Watchdog Mode (WDTE = 1)
83
Power down Operation
84
Watchdog Clock Source
84
Watchdog Timer in Timer Mode (WDTE = 0)
84
Periodic Wakeup from Power down Without an External Oscillator
85
13 Additional Features
87
Software Reset
87
Dual Data Pointers
87
AUXR1 Register
87
14 Flash Program Memory
89
General Description
89
Features
89
Introduction to IAP-Lite
89
Using Flash as Data Storage
89
Flash Memory Control Register
91
Accessing Additional Flash Elements
92
Assembly Language Routine to Erase/Program All or Part of a Page
92
C-Language Routine to Erase/Program All or Part of a Page
92
Erase-Programming Additional Flash Elements
93
Reading Additional Flash Elements
93
Flash Elements Accesable through IAP-Lite
93
Assembly Language Routine to Erase/Program a Flash Element
94
C-Language Routine to Erase/Program a Flash Element
94
C-Language Routine to Read a Flash Element
95
User Configuration Bytes
96
Flash User Configuration Byte 1 (UCFG1)
96
User Security Bytes
97
User Sector Security Bytes (SEC0 ... SEC3)
97
Effects of Security Bits
97
Boot Vector
98
Boot Status
98
Boot Vector (BOOTVEC)
98
Boot Status (BOOTSTAT)
98
15 Instruction Set
99
Instruction Set Summary
99
16 Revision History
103
17 Index
105
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