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Fig 35. Format of Slave Receiver mode.
12.6.4 Slave Transmitter mode
The first byte is received and handled as in the Slave Receiver Mode. However, in this
mode, the direction bit will indicate that the transfer direction is reversed. Serial data is
transmitted via P1.3/SDA while the serial clock is input through P1.2/SCL. START and
STOP conditions are recognized as the beginning and end of a serial transfer. In a given
application, the I
2
I
addresses is detected, an interrupt is requested. When the microcontrollers wishes to
become the bus master, the hardware waits until the bus is free before the master mode is
entered so that a possible slave action is not interrupted. If bus arbitration is lost in the
master mode, the I
slave address in the same serial transfer.
Fig 36. Format of Slave Transmitter mode.
User manual
S
slave address
from Master to Slave
from Slave to Master
2
C-bus may operate as a master and as a slave. In the slave mode, the
C hardware looks for its own slave address and the general call address. If one of these
2
C-bus switches to the slave mode immediately and can detect its own
S
slave address
from Master to Slave
from Slave to Master
Rev. 03 — 7 June 2005
W
A
DATA
A
logic 0 = write
data transferred
logic 1 = read
(n Bytes + acknowledge)
A = acknowledge (SDA LOW)
A = not acknowledge (SDA HIGH)
S = START condition
P = STOP condition
RS = repeated START condition
R
A
DATA
A
logic 0 = write
data transferred
logic 1 = read
(n Bytes + acknowledge)
A = acknowledge (SDA LOW)
A = not acknowledge (SDA HIGH)
S = START condition
P = STOP condition
UM10119
P89LPC938 User manual
DATA
A/A
P/RS
002aaa932
DATA
A
P
002aaa933
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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