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converted, the process will repeat starting with the first selected channel. Additional
conversion results will again cycle through the eight result register pairs, overwriting the
previous results. Continuous conversions continue until terminated by the user. The
channels are converted from LSB to MSB order (in ADINS). This mode is selected by
setting the BURST0 bit in the ADMODA register.
3.2.1.5 Dual channel, continuous conversion mode
This is a variation of the auto scan continuous conversion mode where conversion occurs
on two user-selectable inputs. Any combination of two of the eight input channels can be
selected for conversion. The result of the conversion of the first channel is placed in the
result register pair, AD0DAT0R and AD0DAT0L. The result of the conversion of the second
channel is placed in result register pair, AD0DAT1R and AD0DAT1L. The first channel is
again converted and its result stored in AD0DAT2R and AD0DAT2L. The second channel
is again converted and its result placed in AD0DAT3R and AD0DAT3L, etc. (see
An interrupt is generated, if enabled, after every set of four or eight conversions (user
selectable). This mode is selected by setting the SCC0 bit in the ADMODA register.
Table 9:
Result register
AD0DAT0R/L
AD0DAT1R/L
AD0DAT2R/L
AD0DAT3R/L
AD0DAT4R/L
AD0DAT5R/L
AD0DAT6R/L
AD0DAT7R/L
3.2.1.6 Single step mode
This special mode allows 'single-stepping' in an auto scan conversion mode. Any
combination of the eight input channels can be selected for conversion. After each
channel is converted, an interrupt is generated, if enabled, and the A/D waits for the next
start condition. The result of each channel is placed in the result register which
corresponds to the selected input channel (See
modes. This mode is selected by clearing the BURST0, SCC0, and SCAN0 bits in the
ADMODA register.
3.2.2 Conversion mode selection bits
The A/D uses three bits in ADMODA to select the conversion mode. These mode bits are
summarized in
combinations shown, are undefined.
Table 10:
Burst0
0
0
User manual
Result registers and conversion results for dual channel, continuous conversion
mode
Contains
First channel, first conversion result
Second channel, first conversion result
First channel, second conversion result
Second channel, second conversion result
First channel, third conversion result
Second channel, third conversion result
First channel, fourth conversion result
Second channel, fourth conversion result
Table
10,below. Combinations of the three bits, other than the
Conversion mode bits
SCC0
Scan0
0
0
0
1
Rev. 03 — 7 June 2005
UM10119
P89LPC938 User manual
Table
7). May be used with any of the start
ADC0 conversion mode
Single step
Fixed channel, single
Auto scan, single
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Table
9).
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