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Philips Semiconductors
Table 16:
A/D Mode register B (ADMODB - address A1h) bit description
Bit
Symbol
4
INBND0
7:5
CLK2,CLK1,CLK0 Clock divider to produce the ADC clock. Divides CCLK by the value indicated below.
Table 17:
A/D Input select (ADINS - address A3h) bit allocation
Bit
7
Symbol
AIN07
Reset
0
Table 18:
A/D Input select (ADINS - address A3h) bit description
Bit
Symbol
0
AIN00
1
AIN01
2
AIN02
3
AIN03
4
AIN04
5
AIN05
6
AIN06
7
AIN07
Table 19:
Boundary status register 0 (BNDSTA0 - address FFEDh) bit allocation
Bit
7
Symbol
BST07
Reset
0
User manual
Description
When set = 1, generates an interrupt if the conversion result is inside or equal to the
boundary limits. When cleared = 0, generates an interrupt if the conversion result is
outside the boundary limits.
The resulting ADC clock should be 9 MHz or less. A minimum of 320 kHz is required
to maintain A/D accuracy.
CLK2:0 — Divisor
000 — 1
001 — 2
010 — 3
011 — 4
011 — 5
011 — 6
011 — 7
011 — 8
6
5
AIN06
AIN05
0
0
Description
When set, enables the AD00 pin for sampling and conversion.
When set, enables the AD01 pin for sampling and conversion.
When set, enables the AD02 pin for sampling and conversion.
When set, enables the AD03 pin for sampling and conversion.
When set, enables the AD04 pin for sampling and conversion.
When set, enables the AD05 pin for sampling and conversion.
When set, enables the AD06 pin for sampling and conversion.
When set, enables the AD07 pin for sampling and conversion.
6
5
BST06
BST05
0
0
Rev. 03 — 7 June 2005
...continued
4
3
AIN04
AIN03
0
0
4
3
BST04
BST03
0
0
UM10119
P89LPC938 User manual
2
1
AIN02
AIN01
0
0
2
1
BST02
BST01
0
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
0
AIN00
0
0
BST00
0
29 of 139
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