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P89LPC902
Philips P89LPC902 Manuals
Manuals and User Guides for Philips P89LPC902. We have
1
Philips P89LPC902 manual available for free PDF download: User Manual
Philips P89LPC902 User Manual (114 pages)
8-bit microcontrollers with accelerated two-clock 80C51 core 1KB 3V Low-Power byte-eraseable Flash with 128 Byte RAM
Brand:
Philips
| Category:
Computer Hardware
| Size: 0.89 MB
Table of Contents
Table of Contents
2
1 General Description
7
Pin Configurations
7
Product Comparison
8
Pin Descriptions - P89LPC901
12
Pin Descriptions - P89LPC902
14
Pin Descriptions - P89LPC903
15
Special Function Registers
16
Special Function Registers Table - P89LPC901
16
Special Function Registers Table - P89LPC902
19
Special Function Registers Table - P89LPC903
22
Memory Organization
25
P89LPC901/902/903 Memory Map
25
2 Clocks
27
Enhanced CPU
27
Clock Definitions
27
CPU Clock (OSCCLK)
27
Low Speed Oscillator Option - P89LPC901
27
Medium Speed Oscillator Option - P89LPC901
27
High Speed Oscillator Option - P89LPC901
27
Oscillator Option Selection- P89LPC901
28
Clock Output - P89LPC901
28
On-Chip RC Oscillator Option
28
Using the Crystal Oscillator - P89LPC901
28
Watchdog Oscillator Option
29
External Clock Input Option - P89LPC901
29
On-Chip RC Oscillator TRIM Register
29
Block Diagram of Oscillator Control - P89LPC901
30
Block Diagram of Oscillator Control - P89LPC902
31
CPU Clock (CCLK) Wakeup Delay
32
CPU Clock (CCLK) Modification: DIVM Register
32
Block Diagram of Oscillator Control- P89LPC903
32
Low Power Select (P89LPC901)
33
3 Interrupts
35
Interrupt Priority Structure
35
Interrupt Priority Level
35
Summary of Interrupts - P89LPC901
36
Summary of Interrupts - P89LPC903
36
Summary of Interrupts - P89LPC902
36
External Interrupt Inputs
37
External Interrupt Pin Glitch Suppression
37
Interrupt Sources, Enables, and Power down Wake-Up Sources - P89LPC901
37
Interrupt Sources, Enables, and Power down Wake-Up Sources - P89LPC902
38
Interrupt Sources, Enables, and Power down Wake-Up Sources - P89LPC903
38
4 I/O Ports
39
Port Configurations
39
Quasi-Bidirectional Output Configuration
39
Number of I/O Pins Available
39
Port Output Configuration Settings
39
Open Drain Output Configuration
40
Quasi-Bidirectional Output
40
Open Drain Output
40
Input-Only Configuration
41
Push-Pull Output Configuration
41
Port 0 Analog Functions
41
Input Only
41
Push-Pull Output
41
Additional Port Features
42
Port Output Configuration - P89LPC901
42
Port Output Configuration - P89LPC902
42
Port Output Configuration - P89LPC903
42
5 Timers 0 and 1
45
Timer/Counter Mode Control Register (TMOD)
45
Mode 0
46
Mode 2
46
Mode 3
47
Mode 6 - P89LPC901
47
Timer/Counter Control Register (TCON)
47
Timer/Counter 0 or 1 in Mode 0 (13-Bit Counter)
48
Timer/Counter 0 or 1 in Mode 1 (16-Bit Counter)
48
Timer/Counter 0 or 1 in Mode 2 (8-Bit Auto-Reload)
48
Timer Overflow Toggle Output - P89LPC901
49
Timer/Counter 0 Mode 3 (Two 8-Bit Counters)
49
Timer/Counter 0 in Mode 6 (PWM Auto-Reload), P89LPC901
49
6 Real-Time Clock/System Timer
51
Real-Time Clock Source
51
Real-Time Clock/System Timer Block Diagram
51
Real-Time Clock/System Timer Clock Source - P89LPC901
52
Changing RTCS1-0
53
Real-Time Clock Interrupt/Wake up
53
Reset Sources Affecting the Real-Time Clock
53
Real-Time Clock/System Timer Clock Source - P89LPC902/903
53
RTCCON Register
54
7 Power Monitoring Functions
55
Brownout Detection
55
Power-On Detection
56
Brownout Options
56
Power Reduction Modes
57
Power Control Register (PCON)
58
Power Control Register (PCONA)
59
8 Uart (P89Lpc903)
61
Mode 0
61
Mode 1
61
Mode 2
61
Mode 3
61
SFR Space
62
Baud Rate Generator and Selection
62
Updating the BRGR1 and BRGR0 Sfrs
62
SFR Locations for Uarts
62
Baud Rate Generation for UART
62
Framing Error
63
Break Detect
63
BRGCON Register
63
Baud Rate Generations for UART (Modes 1, 3)
63
Serial Port Control Register (SCON)
64
More about UART Mode 0
65
Serial Port Status Register (SSTAT)
65
More about UART Mode 1
66
Serial Port Mode 0 (Double Buffering Must be Disabled)
66
Serial Port Mode 1 (Only Single Transmit Buffering Case Is Shown)
66
More about UART Modes 2 and 3
67
Framing Error and RI in Modes 2 and 3 with SM2 = 1
67
Break Detect
67
Serial Port Mode 2 or 3 (Only Single Transmit Buffering Case Is Shown)
67
FE and RI When SM2 = 1 in Modes 2 and 3
67
Double Buffering
68
Double Buffering in Different Modes
68
Transmit Interrupts with Double Buffering Enabled (Modes 1, 2 and 3)
68
The 9Th Bit (Bit 8) in Double Buffering (Modes 1, 2 and 3)
69
Transmission with and Without Double Buffering
69
Multiprocessor Communications
70
Automatic Address Recognition
70
9 Reset
73
Power-On Reset Code Execution
73
Block Diagram of Reset
73
Reset Sources Register
74
10 Analog Comparators
75
Comparator Configuration
75
Comparator Control Registers (CMP1 and CMP2)
75
Comparator Input and Output Connections - P89LPC901
76
Comparator Input and Output Connections - P89LPC902
76
Internal Reference Voltage
77
Comparator Interrupt
77
Comparator Input and Output Connections - P89LPC903
77
Comparator Configurations
77
Comparator and Power Reduction Modes
78
Comparator Configuration Example
78
11 Keypad Interrupt (KBI)
79
Keypad Pattern Register- P89LPC901
79
Keypad Pattern Register - P89LPC902
79
Keypad Pattern Register - P89LPC903
80
Keypad Control Register
80
Keypad Interrupt Mask Register (KBM) - P89LPC901
80
Keypad Interrupt Mask Register (KBM)) - P89LPC902
81
Keypad Interrupt Mask Register (KBM)) - P89LPC903
81
12 Watchdog Timer
83
Watchdog Function
83
Watchdog Timer Configuration
83
Feed Sequence
84
Watchdog Prescaler
84
Watchdog Timer Control Register
85
P89LPC901/902/903 Watchdog Timeout Values
86
Watchdog Timer in Watchdog Mode (WDTE = 1)
86
Watchdog Timer in Timer Mode
87
Power down Operation
87
Watchdog Clock Source
87
Watchdog Timer in Timer Mode (WDTE = 0)
87
Periodic Wakeup from Power down Without an External Oscillator
89
13 Additional Features
91
Software Reset
91
Dual Data Pointers
91
AUXR1 Register
91
14 Flash Program Memory
93
General Description
93
Features
93
Introduction to IAP-Lite
93
Using Flash as Data Storage
93
Flash Memory Control Register
95
Assembly Language Routine to Erase/Program All or Part of a Page
95
Accessing Additional Flash Elements
96
C-Language Routine to Erase/Program All or Part of a Page
96
Erase-Programming Additional Flash Elements
97
Reading Additional Flash Elements
97
Flash Elements Accesable through IAP-Lite
97
Assembly Language Routine to Erase/Program a Flash Element
98
C-Language Routine to Erase/Program a Flash Element
98
User Configuration Bytes
99
C-Language Routine to Read a Flash Element
99
Flash User Configuration Byte 1 (UCFG1)
100
User Security Bytes
101
User Sector Security Bytes (SEC0
101
Effects of Security Bits
101
Boot Vector
102
Boot Status
102
Boot Vector (BOOTVEC)
102
Boot Status (BOOTSTAT)
102
15 Instruction Set
103
Instruction Set Summary
103
16 Revision History
107
17 Index
109
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