Philips P89LPC938 User Manual page 91

Single-chip microcontroller
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Philips Semiconductors
CPU clock
DIVIDER
BY 4, 16, 64, 128
SELECT
SPI CONTROL
SPI STATUS REGISTER
Fig 38. SPI block diagram.
The SPI interface has four pins: SPICLK, MOSI, MISO and SS:
Note that even if the SPI is configured as a master (MSTR = 1), it can still be converted to
a slave by driving the SS pin low (if P2.4 is configured as input and SSIG = 0). Should this
happen, the SPIF bit (SPSTAT.7) will be set (see
Typical connections are shown in
Table 87:
Bit
Symbol
Reset
User manual
SPI clock (master)
MSTR
SPEN
SPI
internal
interrupt
data
request
bus
SPICLK, MOSI and MISO are typically tied together between two or more SPI
devices. Data flows from master to slave on the MOSI (Master Out Slave In) pin and
flows from slave to master on the MISO (Master In Slave Out) pin. The SPICLK signal
is output in the master mode and is input in the slave mode. If the SPI system is
disabled, i.e. SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port
functions.
SS is the optional slave select pin. In a typical configuration, an SPI master asserts
one of its port pins to select one SPI device as the current slave. An SPI slave device
uses its SS pin to determine whether it is selected. The SS is ignored if any of the
following conditions are true:
– If the SPI system is disabled, i.e. SPEN (SPCTL.6) = 0 (reset value)
– If the SPI is configured as a master, i.e., MSTR (SPCTL.4) = 1, and P2.4 is
configured as an output (via the P2M1.4 and P2M2.4 SFR bits);
– If the SS pin is ignored, i.e. SSIG (SPCTL.7) bit = 1, this pin is configured for port
functions.
SPI Control register (SPCTL - address E2h) bit allocation
7
6
SSIG
SPEN
0
0
Rev. 03 — 7 June 2005
8-BIT SHIFT REGISTER
READ DATA BUFFER
clock
CLOCK LOGIC
SPI CONTROL REGISTER
Section 13.4 "Mode change on
Figure 39
to
Figure
5
4
3
DORD
MSTR
CPOL
0
0
0
UM10119
P89LPC938 User manual
S
M
M
S
PIN
CONTROL
LOGIC
S
M
002aaa900
41.
2
1
CPHA
SPR1
1
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
MISO
P2.3
MOSI
P2.2
SPICLK
P2.5
SS
P2.4
SS")
0
SPR0
0
91 of 139

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