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Philips Semiconductors
Table 56:
CCU interrupt status encode register (TISE2 - address DEh) bit description
Bit Symbol
Description
2:0 ENCINT.2:0
CCU Interrupt Encode output. When multiple interrupts happen, more than one interrupt flag is set in
CCU Interrupt Flag Register (TIFR2). The encoder output can be read to determine which interrupt is
to be serviced. The user must write a logic 0 to clear the corresponding interrupt flag bit in the TIFR2
register after the corresponding interrupt has been serviced. Refer to
000 — No interrupt pending.
001 — Output Compare Event D interrupt (lowest priority)
010 — Output Compare Event C interrupt.
011 — Output Compare Event B interrupt.
100 — Output Compare Event A interrupt.
101 — Input Capture Event B interrupt.
110 — Input Capture Event A interrupt.
111 — CCU Timer Overflow interrupt (highest priority).
3:7 -
Reserved.
Table 57:
CCU interrupt flag register (TIFR2 - address E9h) bit allocation
Bit
7
Symbol
TOIF2
Reset
0
Table 58:
CCU interrupt flag register (TIFR2 - address E9h) bit description
Bit Symbol
Description
0
TICF2A
Input Capture Channel A Interrupt Flag Bit. Set by hardware when an input capture event is detected.
Cleared by software.
1
TICF2B
Input Capture Channel B Interrupt Flag Bit. Set by hardware when an input capture event is detected.
Cleared by software.
2
-
Reserved for future use. Should not be set to logic 1 by user program.
3
TOCF2A
Output Compare Channel A Interrupt Flag Bit. Set by hardware when the contents of TH2:TL2 match that
of OCRHA:OCRLA. Compare channel A must be enabled in order to generate this interrupt. If EA bit in
IEN0, ECCU bit in IEN1 and TOCIE2A bit are all set, the program counter will vectored to the
corresponding interrupt. Cleared by software.
4
TOCF2B
Output Compare Channel B Interrupt Flag Bit. Set by hardware when the contents of TH2:TL2 match that
of OCRHB:OCRLB. Compare channel B must be enabled in order to generate this interrupt. If EA bit in
IEN0, ECCU bit in IEN1 and TOCIE2B bit are set, the program counter will vectored to the corresponding
interrupt. Cleared by software.
5
TOCF2C
Output Compare Channel C Interrupt Flag Bit. Set by hardware when the contents of TH2:TL2 match that
of OCRHC:OCRLC. Compare channel C must be enabled in order to generate this interrupt. If EA bit in
IEN0, ECCU bit in IEN1 and TOCIE2C bit are all set, the program counter will vectored to the
corresponding interrupt. Cleared by software.
6
TOCF2D
Output Compare Channel D Interrupt Flag Bit. Set by hardware when the contents of TH2:TL2 match that
of OCRHD:OCRLD. Compare channel D must be enabled in order to generate this interrupt. If EA bit in
IEN0, ECCU bit in IEN1 and TOCIE2D bit are all set, the program counter will vectored to the
corresponding interrupt. Cleared by software.
7
TOIF2
CCU Timer Overflow Interrupt Flag bit. Set by hardware on CCU Timer overflow. Cleared by software.
User manual
6
5
TOCF2D
TOCF2C
0
0
Rev. 03 — 7 June 2005
4
3
TOCF2B
TOCF2A
0
0
UM10119
P89LPC938 User manual
Table 58
for TIFR2 description.
2
1
-
TICF2B
x
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
0
TICF2A
0
64 of 139
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