Philips P89LPC938 User Manual page 139

Philips Semiconductors
11.12 More about UART Modes 2 and 3 . . . . . . . . . 71
11.13 Framing error and RI in Modes 2 and 3 with
SM2 = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
11.14 Break detect . . . . . . . . . . . . . . . . . . . . . . . . . . 72
11.15 Double buffering . . . . . . . . . . . . . . . . . . . . . . . 72
11.16 Double buffering in different modes . . . . . . . . 72
11.17 Transmit interrupts with double buffering enabled
(Modes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . 72
11.18 The 9th bit (bit 8) in double buffering (Modes 1, 2,
and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
11.19 Multiprocessor communications . . . . . . . . . . . 74
11.20 Automatic address recognition . . . . . . . . . . . . 75
2
12 I C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
2
12.1 I C data register . . . . . . . . . . . . . . . . . . . . . . . 77
2
12.2 I C slave address register . . . . . . . . . . . . . . . 77
2
12.3 I C control register . . . . . . . . . . . . . . . . . . . . . 78
2
12.4 I C Status register . . . . . . . . . . . . . . . . . . . . . 79
2
12.5 I C SCL duty cycle registers I2SCLH and
I2SCLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
2
12.6 I C operation modes. . . . . . . . . . . . . . . . . . . . 80
12.6.1 Master Transmitter mode . . . . . . . . . . . . . . . . 80
12.6.2 Master Receiver mode . . . . . . . . . . . . . . . . . . 81
12.6.3 Slave Receiver mode . . . . . . . . . . . . . . . . . . . 82
12.6.4 Slave Transmitter mode . . . . . . . . . . . . . . . . . 83
13 Serial Peripheral Interface (SPI) . . . . . . . . . . . 90
13.1 Configuring the SPI . . . . . . . . . . . . . . . . . . . . 94
13.2 Additional considerations for a slave . . . . . . . 95
13.3 Additional considerations for a master . . . . . . 95
13.4 Mode change on SS . . . . . . . . . . . . . . . . . . . . 95
13.5 Write collision . . . . . . . . . . . . . . . . . . . . . . . . . 96
13.6 Data mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
13.7 SPI clock prescaler select. . . . . . . . . . . . . . . 100
14 Analog comparators . . . . . . . . . . . . . . . . . . . 100
14.1 Comparator configuration . . . . . . . . . . . . . . . 100
14.2 Internal reference voltage . . . . . . . . . . . . . . . 102
14.3 Comparator input pins . . . . . . . . . . . . . . . . . 102
14.4 Comparator interrupt . . . . . . . . . . . . . . . . . . 102
14.5 Comparators and power reduction modes . . 102
14.6 Comparators configuration example . . . . . . . 103
15 Keypad interrupt (KBI). . . . . . . . . . . . . . . . . . 104
16 Watchdog timer (WDT) . . . . . . . . . . . . . . . . . 105
16.1 Watchdog function . . . . . . . . . . . . . . . . . . . . 105
16.2 Feed sequence . . . . . . . . . . . . . . . . . . . . . . . 106
16.3 Watchdog clock source . . . . . . . . . . . . . . . . 109
16.4 Watchdog Timer in Timer mode . . . . . . . . . . 110
16.5 Power-down operation . . . . . . . . . . . . . . . . . 111
16.6 Periodic wake-up from power-down without an
external oscillator . . . . . . . . . . . . . . . . . . . . . 111
17 Additional features . . . . . . . . . . . . . . . . . . . . 111
17.1 Software reset . . . . . . . . . . . . . . . . . . . . . . . 112
17.2 Dual Data Pointers . . . . . . . . . . . . . . . . . . . . 112
18 Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . 112
18.1 Data EEPROM read. . . . . . . . . . . . . . . . . . . 113
18.2 Data EEPROM write . . . . . . . . . . . . . . . . . . 114
18.3 Hardware reset . . . . . . . . . . . . . . . . . . . . . . 114
18.4 Multiple writes to the DEEDAT register . . . . 114
18.5 Sequences of writes to DEECON and DEEDAT
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
18.6 Data EEPROM Row Fill . . . . . . . . . . . . . . . . 114
18.7 Data EEPROM Block Fill . . . . . . . . . . . . . . . 115
19 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 115
19.1 General description . . . . . . . . . . . . . . . . . . . 115
19.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
19.3 Flash programming and erase . . . . . . . . . . . 116
19.4 Using Flash as data storage: IAP-Lite . . . . . 116
19.5 In-circuit programming (ICP) . . . . . . . . . . . . 120
19.6 ISP and IAP capabilities of the P89LPC938 120
19.7 Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . 120
19.8 Power on reset code execution . . . . . . . . . . 120
19.9 Hardware activation of Boot Loader. . . . . . . 121
19.10 In-system programming (ISP) . . . . . . . . . . . 121
19.11 Using the In-system programming (ISP) . . . 122
19.12 In-application programming (IAP) . . . . . . . . 125
19.13 IAP authorization key . . . . . . . . . . . . . . . . . . 126
19.14 Flash write enable . . . . . . . . . . . . . . . . . . . . 126
19.15 Configuration byte protection . . . . . . . . . . . . 126
19.16 IAP error status . . . . . . . . . . . . . . . . . . . . . . 127
19.17 User configuration bytes . . . . . . . . . . . . . . . 130
19.18 User security bytes . . . . . . . . . . . . . . . . . . . 131
19.19 Boot Vector register . . . . . . . . . . . . . . . . . . . 132
19.20 Boot status register . . . . . . . . . . . . . . . . . . . 132
20 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . 134
21 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 137
22 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 137
© Koninklijke Philips Electronics N.V. 2005
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Published in the Netherlands
UM10119
P89LPC938 User manual
Date of release: 7 June 2005