Philips P89LPC938 User Manual page 42

Philips Semiconductors
Table 28: Power Control register (PCON - address 87h) bit allocation
Bit 7
Symbol SMOD1
Reset 0
Table 29: Power Control register (PCON - address 87h) bit description
Bit Symbol
0 PMOD0
1 PMOD1
2 GF0
3 GF1
4 BOI
5 BOPD
6 SMOD0
7 SMOD1
Table 30: Power Control register A (PCONA - address B5h) bit allocation
Bit 7
Symbol RTCPD
Reset 0
Table 31: Power Control register A (PCONA - address B5h) bit description
Bit Symbol
0 CCUPD
1 SPD
2 SPPD
3 I2PD
User manual
6 5
SMOD0 BOPD
0 0
Description
Power Reduction Mode (see
General Purpose Flag 0. May be read or written by user software, but has no effect
on operation
General Purpose Flag 1. May be read or written by user software, but has no effect
on operation
Brownout Detect Interrupt Enable. When logic 1, Brownout Detection will generate a
interrupt. When logic 0, Brownout Detection will cause a reset
Brownout Detect power-down. When logic 1, Brownout Detect is powered down and
therefore disabled. When logic 0, Brownout Detect is enabled. (Note: BOPD must
be logic 0 before any programming or erasing commands can be issued. Otherwise
these commands will be aborted.)
Framing Error Location:
•
When logic 0, bit 7 of SCON is accessed as SM0 for the UART.
•
When logic 1, bit 7 of SCON is accessed as the framing error status (FE) for the
UART
Double Baud Rate bit for the serial port (UART) when Timer 1 is used as the baud
rate source. When logic 1, the Timer 1 overflow rate is supplied to the UART. When
logic 0, the Timer 1 overflow rate is divided by two before being supplied to the
UART. (See Section
6 5
DEEPD VCPD
0 0
Description
Compare/Capture Unit (CCU) power-down: When logic 1, the internal clock to the
CCU is disabled. Note that in either Power-down mode or Total Power-down mode,
the CCU clock will be disabled regardless of this bit. (Note: This bit is overridden by
the CCUDIS bit in FCFG1. If CCUDIS = 1, CCU is powered down.)
Serial Port (UART) power-down: When logic 1, the internal clock to the UART is
disabled. Note that in either Power-down mode or Total Power-down mode, the
UART clock will be disabled regardless of this bit.
SPI power-down: When logic 1, the internal clock to the SPI is disabled. Note that in
either Power-down mode or Total Power-down mode, the SPI clock will be disabled
regardless of this bit.
2
I C power-down: When logic 1, the internal clock to the I
that in either Power-down mode or Total Power-down mode, the I
disabled regardless of this bit.
Rev. 03 — 7 June 2005
4 3
BOI GF1
0 0
Section 6.3)
11)
4 3
ADPD I2PD
0 0
UM10119
P89LPC938 User manual
2 1
GF0 PMOD1
0 0
2 1
SPPD SPD
0 0
2
C-bus is disabled. Note
2
C clock will be
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
0
PMOD0
0
0
CCUPD
0
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