Features - Texas Instruments TMS320C6000 Reference Manual

Multichannel Buffered Serial Port (McBSP)
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Features

SPRU580C
This document describes the operation of the multichannel buffered serial port
(McBSP) in the digital signal processors (DSPs) of the TMS320C6000 DSP
family.
The McBSP provides these functions:
Full-duplex communication
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Double-buffered data registers, which allow a continuous data stream
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Independent framing and clocking for receive and transmit
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Direct interface to industry-standard codecs, analog interface chips (AICs),
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and other serially connected analog-to-digital (A/D) and digital-to-analog
(D/A) devices
External shift clock or an internal, programmable frequency shift clock for
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data transfer
In addition, the McBSP has the following capabilities:
Direct interface to:
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T1/E1 framers
J
MVIP switching compatible and ST-BUS compliant devices including:
J
H MVIP framers
H H.100 framers
H SCSA framers
IOM-2 compliant devices
J
AC97 compliant devices (The necessary multi phase frame
J
synchronization capability is provided.)
IIS compliant devices
J
SPI devices
J
Multichannel transmit and receive of up to 128 channels
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A wide selection of data sizes, including 8, 12, 16, 20, 24, and 32 bits
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µ-Law and A-Law companding
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8-bit data transfers with the option of LSB or MSB first
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Programmable polarity for both frame synchronization and data clocks
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Highly programmable internal clock and frame generation
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Multichannel Buffered Serial Port (McBSP) 11