Registers
Table 33. Pin Control Register (PCR) Field Descriptions (Continued)
Bit
†
field
3
FSXP
2
FSRP
1
CLKXP
0
CLKRP
†
For CSL implementation, use the notation MCBSP_PCR_field_symval
114
Multichannel Buffered Serial Port (McBSP)
†
Value
symval
ACTIVEHIGH
0
ACTIVELOW
1
ACTIVEHIGH
0
ACTIVELOW
1
RISING
0
FALLING
1
FALLING
0
RISING
1
Description
Transmit frame-synchronization polarity bit.
Transmit frame-synchronization pulse is active high.
Transmit frame-synchronization pulse is active low.
Receive frame-synchronization polarity bit.
Receive frame-synchronization pulse is active high.
Receive frame-synchronization pulse is active low.
Transmit clock polarity bit.
Transmit data sampled on rising edge of CLKX.
Transmit data sampled on falling edge of CLKX.
Receive clock polarity bit.
Receive data sampled on falling edge of CLKR.
Receive data sampled on rising edge of CLKR.
SPRU580C
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