Spi Protocol: Clkstp; Spi Configuration: Mcbsp As The Master; Spi Configuration: Mcbsp As The Slave - Texas Instruments TMS320C6000 Reference Manual

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SPI Protocol: CLKSTP

Figure 44.

SPI Configuration: McBSP as the Master

Figure 45.

SPI Configuration: McBSP as the Slave

SPRU580C
A system conforming to the SPI protocol has a master-slave configuration.
The SPI protocol is a 4-wire interface composed of serial data in (master in
slave out or MISO), serial data out (master out slave in or MOSI), shift clock
(SCK), and an active (low) slave enable (SS) signal. Communication between
the master and the slave is determined by the presence or absence of the
master clock. Data transfer is initiated by the detection of the master clock and
is terminated on absence of the master clock. The slave has to be enabled
during this period of transfer. When the McBSP is the master, the slave enable
is derived from the master transmit frame sync pulse (FSX). Example block
diagrams of the McBSP as a master and as a slave are shown in Figure 44 and
Figure 45, respectively.
McBSP master
McBSP slave
SPI compliant
slave
CLKX
SCK
DX
MOSI
DR
MISO
FSX
SS
SPI compliant
master
CLKX
SCK
DX
MISO
DR
MOSI
FSX
SS
Multichannel Buffered Serial Port (McBSP)
SPI Protocol: CLKSTP
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