Texas Instruments TMS320C6000 Reference Manual page 91

Table 22. Serial Port Control Register (SPCR) Field Descriptions (Continued)
Bit †
field
21−20 XINTM
19 XSYNCERR
18 XEMPTY
17 XRDY
16 XRST
15 DLB
†
For CSL implementation, use the notation MCBSP_SPCR_field_symval
SPRU580C
† Value Description
symval
0−3h Transmit interrupt (XINT) mode bit.
XRDY 0 XINT is driven by XRDY (end-of-word) and end-of-frame in
A-bis mode.
EOS 1h XINT is generated by end-of-block or end-of-frame in
multichannel operation.
FRM 2h XINT is generated by a new frame synchronization.
XSYNCERR 3h XINT is generated by XSYNCERR.
Transmit synchronization error bit. Writing a 1 to XSYNCERR
sets the error condition when the transmitter is enabled
(XRST = 1). Thus, it is used mainly for testing purposes or if
this operation is desired.
NO 0 No synchronization error is detected.
YES 1 Synchronization error is detected.
Transmit shift register empty bit.
YES 0 XSR is empty.
NO 1 XSR is not empty.
Transmitter ready bit.
NO 0 Transmitter is not ready.
YES 1 Transmitter is ready for new data in DXR.
Transmitter reset bit resets or enables the transmitter.
YES 0 Serial port transmitter is disabled and in reset state.
NO 1 Serial port transmitter is enabled.
Digital loop back mode enable bit.
OFF 0 Digital loop back mode is disabled.
ON 1 Digital loop back mode is enabled.
Multichannel Buffered Serial Port (McBSP)
Registers
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