Frame Synchronization Ignore; Frame Sync Ignore And Unexpected Frame Sync Pulses - Texas Instruments TMS320C6000 Reference Manual

5.4

Frame Synchronization Ignore

5.4.1

Frame Sync Ignore and Unexpected Frame Sync Pulses

SPRU580C
The McBSP can be configured to ignore transmit and receive frame
synchronization pulses. The (R/X)FIG bit in (R/X)CR can be cleared to 0 to
recognize frame sync pulses, or it can be set to 1 to ignore frame sync pulses.
In this way, you can use (R/X)FIG either to pack data, if operating at maximum
frame frequency, or to ignore unexpected frame sync pulses.
RFIG and XFIG are used to ignore unexpected internal or external frame sync
pulses. Any frame sync pulse is considered unexpected if it occurs one or more
bit clocks earlier than the programmed data delay from the end of the previous
frame specified by ((R/X)DATDLY). Setting the frame ignore bits to 1 causes
the serial port to ignore these unexpected frame sync signals.
In reception, if not ignored (RFIG = 0), an unexpected FSR pulse discards the
contents of RSR in favor of the incoming data. Therefore, if RFIG = 0, an
unexpected frame synchronization pulse aborts the current data transfer, sets
RSYNCERR in SPCR to 1, and begins the reception of a new data element.
When RFIG = 1, the unexpected frame sync pulses are ignored.
In transmission, if not ignored (XFIG = 0), an unexpected FSX pulse aborts the
ongoing transmission, sets the XSYNCERR bit in SPCR to 1, and reinitiates
transmission of the current element that was aborted. When XFIG = 1,
unexpected frame sync signals are ignored.
Figure 24 shows that element B is interrupted by an unexpected frame sync
pulse when (R/X)FIG = 0. The reception of B is aborted (B is lost), and a new
data element (C) is received after the appropriate data delay. This condition
causes a receive synchronization error and thus sets the RSYNCERR bit.
However, for transmission, the transmission of B is aborted and the same data
(B) is retransmitted after the appropriate data delay. This condition is a transmit
synchronization error and thus sets the XSYNCERR bit. Synchronization
errors are discussed in sections 5.5.2 and 5.5.5.
Multichannel Buffered Serial Port (McBSP)
McBSP Standard Operation
47