Stopping Clocks; Frame Sync Generation - Texas Instruments TMS320C6000 Reference Manual

Clocks, Frames, and Data
4.3.8

Stopping Clocks

4.4

Frame Sync Generation

28 Multichannel Buffered Serial Port (McBSP)
There are two methods to stop serial clocks between data transfers. One
method is using the SPI CLKSTP mode where clocks are stopped between
single-element transfers. This is described in section 9.
The other method is when the clocks are inputs to the McBSP (CLKXM or
CLKRM = 0) and the McBSP operates in non-SPI mode. This means that
clocks can be stopped between data transfers. If the external device stops the
serial clock between data transfers, the McBSP interprets it as a slow-down
serial clock. Ensure that there are no glitches on the CLK(R/X) lines as the
McBSP may interpret them as clock-edge transitions. Restarting the serial
clock is equivalent to a normal clock transition after a slow CLK(R/X) cycle.
Note that just as in normal operations, transmit under flow (XEMPTY) may
occur if the DXR is not properly serviced at least three CLKX cycles before the
next frame sync. Therefore if the serial clock is stopped before DXR is properly
serviced, the external device needs to restart the clock at least three CLKX
cycles before the next frame sync to allow the DXR write to be properly
synchronized. Refer to Figure 34 (page 56) for a graphical explanation on
when DXR needs to be written to avoid underflow.
Data frame synchronization is independently programmable for the receiver
and the transmitter for all data delay values. When set to 1, the FRST bit in
SPCR activates the frame generation logic to generate frame sync signals,
provided that FSGM = 1 in SRGR. The frame sync programming options are:
A frame pulse with a programmable period between sync pulses and a
-
programmable active width specified in the sample rate generator register
(SRGR).
The transmitter can trigger its own frame sync signal that is generated by
-
a DXR-to-XSR copy. This causes a frame sync to occur on every
DXR-to-XSR copy. The data delays can be programmed as required.
However, maximum packet frequency cannot be achieved in this method
for data delays of 1 and 2.
Both the receiver and transmitter can independently select an external frame
-
synchronization on the FSR and FSX pins, respectively.
SPRU580C