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The S–CPU does the following.
–
Controls the host system and video control board communication,
through the logic on the I/O board.
–
Reads and operates the keys, display, and all indicators on the
control panel except the jam indicators. (The jam indicators are
operated by the dc control board.)
–
Controls read/write access to the electrically erasable programmable
read-only memory (EEPROM). The EEPROM is referred to as
NVRAM by the control panel display (nonvolatile random-access
memory).
–
Operates the dc control board through 14 logic level signals shown
in Figure 1–12 and Figure 1–14.
–
Generates refresh clock pulses that maintain data bits stored in
dynamic random-access memory (DRAM).
–
Controls all communication between the M–CPU and elements on
the video control board.
•
Gate array 1 (GA1) controls the direct memory access (DMA) process
to the DRAM. The DRAM is accessed by the dc control board and by
devices on the video control boards.
•
Gate array 2 (GA2) controls the transfer timing of the dot pattern data
to the dc control board.
•
The DRAM is divided into the following three fields (the size of which
is adjustable through the control panel setup menu):
–
The page or input buffer contains data received from the host
system.
–
The page memory contains the image data bitmap or dot pattern
data.
–
The font cache memory contains processed fonts.
•
The read-only memory (ROM) holds the image data that makes up the
internal fonts and stores the firmware operating programs of the video
control board.
1–18 DEClaser 2200 Printer Service Guide
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