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The Q (bandwidth) is set by the resistance of the PIN diode CR18. A more detailed
schematic of the Second LC Pole circuit is shown in Figure 7.
Figure 7. Second LC Pole Circuit, Simplified Schematic
The LC filter pole comprises an inductor (L14) in parallel with four capacitors: C48, C46
(LC CENTER), and the series combination of C49* and C81*. The parallel circuit is driven
through PIN diode CR18, which functions as a variable resistor. The BW7 line sets the
current through CR18. Higher resistance results in narrower bandwidth.
C67 and L15 tune out the case capacitance of CR18. R55* sets the 100 kHz bandwidth when
CR18 is back biased (that is, highest resistance). CR17 is controlled by the LC adjustment
R35 and compensates for losses in the parallel resonant circuit. In the First LC Pole circuit,
fixed resistor R29* replaces CR17.
Low gain in one of the poles in the 100 kHz bandwidth is caused by:
1. Broken or cracked metalized-glass inductor (often intermittent).
2. The pole being centered at some frequency other than 21.4 MHz.
3. Insufficient feedback from the buffer amplifier.
4. Defective buffer amplifier that is loading the circuit.
If the 10 kHz bandwidth amplitude is correct, but that of the 300 kHz bandwidth is too
low, either C66 or C67 is not properly adjusted. If the 300 kHz amplitude is too high, the
four LC poles are not tuned close enough to the same frequency. In either case, refer to the
Performance Tests and Adjustments Manual.
Figure 6. LC Pole, Equivalent Circuit
C R 1 8
C 6 7
L C D I P
L 1 5
,
c 4 9
-
L 1 4
C 8 1
I
I
-
-
-
8
L C P O L E )
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