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and AY at a constant rate such that the output becomes X + AX and Y + AY; that is, "new
X Register @
U5 and U6 form a lo-bit X Position Register. When a new X position is present on lines
LDX causes U5 and U6 to be loaded with the value of BO-B9. These 10 bits then become the
X position input to the X DAC. Characters are drawn by changing only bits 1, 2, and 3 of the
X Position register and bits 1 through 4 of the Y Position Register. Strokes of a character
are described by a series of X and Y values sent to the Line Generator on the Digital Storage
Bus. B4-B6 of the Digital Storage Bus carry the series of X values. When the next X value is
present on B4-B6, the CHAR line is held high and a positive-going edge on LDCHAR caused
U5 to be loaded with the new values for bits 1 through 3 of the X position.
X DAC @
The output of U5 and U6 are the X position input to U4, the X DAC. U4 is a lo-bit
multiplying DAC whose output current depends on the digital input code and the voltage
at VREF (pin 15). This output current is the analog X position sent to the X Summing
Amplifier. The inputs of U4 are clamped to a maximum of +3.6 V by diodes CR1 through
X Summing Amplifier GJ
The X Summing Amplifier receives the next X position from the X DAC, the present X
position from the X Integrator, and an X position shift from the Expand Register. The
three signals are summed to give AX = "next X" + "X shift" - "present X." "X shift" is a
binary signal of 0 V or +5 V, and the amount of shift is adjusted by X EXP potentiometer
screen lower left). X GAIN potentiometer R4, the X line generator gain adjustment, varies
the magnitude of the X line generator output. R4 also has an effect on the accuracy of line
positions. XLL potentiometer R6, the X long line adjust, is used to adjust line position
accuracy. (See Integrator description.)
X Sample and Hold @I
The AX value from the Summing Amplifier is held for constant input to the Integrator by
the X Sample and Hold circuit. Sampling occurs during the setup period, which lasts 1 ps.
Holding occurs during the drawing period, which lasts 4 ps or 19 ps. Q2 and Q3 are on
during the sample mode and are driven by the SMPL line. Ql and Q4 are on during the hold
mode and are driven by the HLDX line. (See Figure 2.) Q6 is a dual FET used to provide a
high-impedance input to U2. Capacitor C23 is the holding capacitor.
2 A3A3
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