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Pipeline Registers @ @
The Pipeline Registers, U24 and U28, hold instructions from the Program ROM for 125 ns
during execution.
Addressable Flip-Flops @
U21 and U23 contain 16 flip-flops that may be individually set and cleared. These flip-flops
control signals for the Input Section and CRT Driver Section of A3 Digital Storage. The
Input Section includes A3A8 Analog-Digital Converter and A3A9 Track and Hold. The CRT
Driver Section includes A3Al Trigger, A3A2 Intensity Control, and A3A3 Line Generator.
The flip-flops also control flags and memory control lines for the Processor Section, which
includes A3A4 Memory, A3A5 Data Manipulator, A3A6 Main Control, and A3A7 Interface.
flops. U29 contains buffers to output flag and timer signals onto the Digital Storage Bus.
Control Pulses @
U26 decodes eight control pulses based on the instruction in the Pipeline Register U24. U25A
is a flip-flop that is set and cleared by the signals decoded by U26. U26 controls the reset of
peak detectors in the Input Section of A3 Digital Storage.
Dual Timer @I
about 20 /.Ls, is used in the digital peak detection algorithm.
RAM Chip Enable Generator @
U22 generates chip enable timing for A3A4 Memory. It delays execution of program
instructions l-1/2 states (182.5 ns) to allow addresses to settle.
2 A3A6
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